Abstract: A charge self-compensation technology is proposed in this paper to lower the active power and improve the performance of domino circuits.Domino circuits with different structures of pull-up network (PUN) and pull-down network (PND) are designed using charge self-compensation technology and are simulated based on 65,45,and 32nm BSIM4 SPICE models by the HSPICE tools.The simulation results show that this technology is effective for high performance and low power operation.The power-delay product (PDP) is reduced by up to 42.37% compared to standard domino circuits.Moreover,a novel method for power distribution is introduced.With this method,taking a Zipper CMOS full-adder in 45nm technology as an example,the paths for charge self-compensation is optimized to minimize the power.Finally,the influence of W/L of nMOS and pMOS in the path for charge self-compensation and input of the circuits on this technology is analyzed thoroughly.

Key words: path for charge self-compensation, power-delay product (PDP), Zipper CMOS full-adder, domino circuits