Abstract: A novel clock and data recovery circuit has been designed to implement a digital visual interface (DVI) receiver.A flexible buffer was placed between the over-sampler and DPLL.Not only was 10bits data recovery implemented,but also the frequency of sampling clock was reduced to 2.5 times of the data frequency.The phase verification for 10bit parallel data by DPLL increases the accuracy rate of judgment and improves the bit error rate.The receiver has been fabricated with an SMIC 0.18μm CMOS process.The testing results show that the maximum peak-peak and RMS jitters of the output system clock are 183ps and 24ps,respectively,under the measuring condition that the data rate is 1.65Gbps/ch for inputting a UXGA pixel data signal with 2m cable.

Key words: DVI, clock and data recovery, over-sampler, DPLL