Abstract: Dual-modulus prescalers (DMP) for RF receivers are studied.An improved D-latch is proposed to increase the speed and the driving capability of the DMP.A novel D-latch architecture integrated with ‘OR’ logic is proposed to decrease the complexity of the circuit.A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process.The programmable & pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process.The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable & pulse swallow divider.

Key words: PLL, frequency synthesizer, DMP, programmable & pulse swallow divider