Abstract: A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed.In the design,the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure,and biasing all the cells with the same voltage bias source,which requires careful layout design and large capacitors.In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range.The ADC was implemented in a 0.18μm 4M-1P CMOS process,and the experimental results indicate that it consumes only 7mW,which is much less than general pipeline ADCs.The ADC was used in a 300000 pixels CMOS image sensor.

Key words: pipeline ADC, low power design, CMOS image sensor, large signal processing range