Fig1.  (Color online) Process flow chart. (a) Insulating layer/PCM/sacrificial layer deposition. (b) Lithography. (c) Dry etching of PCM/sacrificial layer. (d) Electrode film sputtering. (e) Lithography. (f) Dry etching of electrode film. (g) Wet etching of sacrificial layer. (h) Additional PCM NW removal. (i) Lift-off. (j) Lithography. (k) Dry etching of tungsten film. (l) Device passivation and the formation of testing pads.

Fig2.  (Color online) The results of the process. (a) Top-view of PMMA resist as both positive and negative resist in the same fabrication process. (b) Top-view and (c) oblique-view of negative PMMA resist before dry etching. (d) Top-view of negative PMMA resist blown down with the nitrogen gun. (e) GST/SiO$_{2}$ NWs after dry etching with single line layout. (f) Improved lithography layout. (g) Tungsten film of 60 nm covering SiO$_{2}$/GST NWs after dry etching with H-shaped layout. (h) After sacrificial layer removal. (i) Positive PMMA resist with window-gap based layout. (j) PCM node after lift-off. (k) Photoresist mask covering PCM node for device separation.

Fig3.  Process results of window-gap based layout. (a), (b) Schematic diagram of the edge shrinking effect. (c) Tungsten after dry etch with different window-gap size and exposure dose.

Fig4.  (a) $I$-$V$ (current-sweeping mode) characteristic. The threshold voltage is 3.45 V and the corresponding pulse current is 23.6 $\mu $A. (b) The pulsed $R$-$V$ characteristic (RESET and SET processes). $V_{\rm set}$ $=$ 4.3 V with the pulse width of 100 ns (pulse falling 3 ns). $V_{\rm reset}$ $=$ 6.8 V with the pulse width of 40 ns (pulse falling 3 ns).