PAPERS
Abstract: A high-resolution, 200kHz signal bandwidth, third-order single-loop single-bit ΣΔ modulator used in low-IF GSM receivers is presented.The modulator is implemented with fully differential switched capacitor circuits in standard 0.6μm 2P2M CMOS technology.The modulator uses two balanced reference voltages of ±1V, and is driven by a single 26MHz clock signal.The measurement results show that, with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range, a 71.8dB peak SNDR, and a 73.9dB peak SNR in the signal bandwidth of 200kHz.The modulator dissipates 15mW static power from a single 5V supply.
Key words: sigma-delta modulator, analog-to-digital conversion, switched-capacitor, operational amplifiers
Article views: 2986 Times PDF downloads: 1012 Times Cited by: 0 Times
Received: 18 August 2015 Revised: 15 October 2007 Online: Published: 01 February 2008
| Citation: |
Yang Pei, Yin Xiumei, Yang Huazhong. An 80dB Dynamic Range ΣΔ Modulator for Low-IF GSM Receivers[J]. Journal of Semiconductors, 2008, 29(2): 256-261.
****
Yang P, Yin X M, Yang H Z. An 80dB Dynamic Range ΣΔ Modulator for Low-IF GSM Receivers[J]. J. Semicond., 2008, 29(2): 256.
|
Journal of Semiconductors © 2017 All Rights Reserved 京ICP備05085259號(hào)-2