Chin. J. Semicond. > 2007, Volume 28?>?Issue 10?> 1642-1646

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A High-Speed High-Resolution Sample-and-Hold Circuit

Yang Bin, Yin Xiumei and Yang Huazhong

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Abstract: A high performance CMOS sample and hold (S/H) circuit for use in the front end of a 12bit 100MS/s ADC is presented.It achieves a 108dB spurious-free dynamic range and 77dB signal-to-noise ratio over the Nyquist band at a 100MHz sampling frequency with a 3V power supply.An analysis model for the S/H circuit is built to capture the switching effect.The impact of the switches’ arrangement is also addressed.The leakage in a conventional bootstrapped switch is analyzed and some improvements are made,enhancing the linearity significantly.

Key words: sample-and-hold circuit,  bootstrapped switch,  gain-boosting operational amplifier

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    Received: 18 August 2015 Revised: 29 April 2007 Online: Published: 01 October 2007

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      Yang Bin, Yin Xiumei, Yang Huazhong. A High-Speed High-Resolution Sample-and-Hold Circuit[J]. Journal of Semiconductors, 2007, 28(10): 1642-1646. ****Yang B, Yin X M, Yang H Z. A High-Speed High-Resolution Sample-and-Hold Circuit[J]. Chin. J. Semicond., 2007, 28(10): 1642.
      Citation:
      Yang Bin, Yin Xiumei, Yang Huazhong. A High-Speed High-Resolution Sample-and-Hold Circuit[J]. Journal of Semiconductors, 2007, 28(10): 1642-1646. ****
      Yang B, Yin X M, Yang H Z. A High-Speed High-Resolution Sample-and-Hold Circuit[J]. Chin. J. Semicond., 2007, 28(10): 1642.

      A High-Speed High-Resolution Sample-and-Hold Circuit

      • Department of Electronic Engineering, Tsinghua University,Beijing 100084, China

      • Department of Electronic Engineering, Tsinghua University,Beijing 100084, China

      • Department of Electronic Engineering, Tsinghua University,Beijing 100084, China

      • Received Date: 2015-08-18
      • Accepted Date: 2007-03-14
      • Revised Date: 2007-04-29
      • Published Date: 2007-09-26

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