Abstract: An improved three-stage amplifier topology with a new frequency compensation technique is proposed.It can produce two left-half-plane zeros to compensate the two non-dominant poles and the dominant pole by adjusting the compensation factor,giving the amplifier very large bandwidth and good phase margin.Moreover,the amplifier requires only one small compensation capacitor and does not consume much power when driving a large load capacitor.A GBW of 25MHz,DC gain of 100dB,PM of 90°,and power dissipation of 0.625mW can be achieved for a load capacitor of 100pF with a single Miller compensation capacitance of 2pF and a compensation factor of 4 in 0.5μm CMOS technology.

Key words: single Miller capacitor, three-stage amplifier with low voltage, DPZC