Abstract: A programmable multi-modulus frequency divider is designed and implemented in a 0.35μm CMOS process.The multi-modulus frequency divider is a single chip with two dividers in series, which are divided by 4 or 5 prescaler and by 128~255 multi-modulus frequency divider.In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128~255 multi-modulus frequency divider.The chip is designed with ESD protected I/O PAD.The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals.The dual-modulus prescaler consumes 11mA of current while the 128~255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply.The core area of the die without PAD is 0.65mm×0.3mm.This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers.To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

Key words: prescaler, frequency divider, programmable, multi-modulus, frequency synthesizer