Abstract: Transient characteristic analysis of a CMOS circuit based on a double-gate dual-strained channel SOI MOSFET with the effective gate length scaling down to 25nm is presented.As a result of simulations,by the adoption of a single-gate (SG) control mechanism,the conversion time from logic 1 to logic 0 is shorter for conventional strained-Si CMOS than unstrained CMOS.Furthermore,the conversion time from logic 0 to logic 1 can be reduced by the application of a strained-SiGe CMOS circuit.However,the CMOS circuit based on the novel structure can reduce tHL and tLH simultaneously.By the adoption of a double-gate (DG) control mechanism,the conversion time of the CMOS circuit shows a dramatic reduction compared with the SG control mechanism and the performance of the CMOS circuit can be improved significantly.

Key words: double-gate, dual-strained-channel, CMOS