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J. Semicond. > 2008, Volume 29?>?Issue 2?> 214-218

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On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method

Sun Weifeng, Wu Hong, Shi Longxing, Yi Yangbo and Li Haisong

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Abstract: The on-resistance degradations of the p-type lateral extended drain MOS transistor (pLEDMOS) with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated.This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor.An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide.The effects are analyzed with a MEDICI simulator.

Key words: pLEDMOS, on-resistance degradation, hot electron injection and trapping, thick gate oxide

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    Received: 18 August 2015 Revised: 20 September 2007 Online: Published: 01 February 2008

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      Sun Weifeng, Wu Hong, Shi Longxing, Yi Yangbo, Li Haisong. On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method[J]. Journal of Semiconductors, 2008, 29(2): 214-218. ****Sun W F, Wu H, Shi L X, Yi Y B, Li H S. On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method[J]. J. Semicond., 2008, 29(2): 214.
      Citation:
      Sun Weifeng, Wu Hong, Shi Longxing, Yi Yangbo, Li Haisong. On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method[J]. Journal of Semiconductors, 2008, 29(2): 214-218. ****
      Sun W F, Wu H, Shi L X, Yi Y B, Li H S. On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method[J]. J. Semicond., 2008, 29(2): 214.

      On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method

      • National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

      • National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

      • National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

      • National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

      • National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

      • Received Date: 2015-08-18
      • Accepted Date: 2007-08-13
      • Revised Date: 2007-09-20
      • Published Date: 2008-01-31

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