A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

Quan Pan; Xiongshi Luo; Zhenghao Li; Zhengzhe Jia; Fuzhan Chen; Xuewei Ding; C. Patrick Yue

doi:10.1088/1674-4926/43/7/072401

J. Semicond. > 2022, Volume 43?>?Issue 7?> 072401

ARTICLES

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

Quan Pan^1,, Xiongshi Luo¹, Zhenghao Li¹, Zhengzhe Jia¹, Fuzhan Chen^{1, 2}, Xuewei Ding³ and C. Patrick Yue²

+ Author Affiliations

1. School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen 518055, China
2. Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong SAR, China
3. ZTE Microelectronics, Shenzhen 518055, China

Author Bio:

Quan Pan (S’08–M’14) received his B.S. degree in Electrical Engineering (EE) at University of Science and Technology of China (USTC) in 2005, and his Ph.D. degree in Electronics and Computer Engineering (ECE) at the Hong Kong University of Science and Technology (HKUST) in 2014. He is an Assistant Professor at School of Microelectronics, Southern University of Science and Technology since 2018. His research interests include high-speed optical transceiver, wireless, and wireline circuit design.

Xiongshi Luo received B.S. degrees in microelectronics science and engineering from Southern University of Science and Technology, Shenzhen, China, in 2019. He is currently pursuing a M.S. degree at the same university. His research interests include high-speed serial links and optical interconnects.

Zhenghao Li received B.S. degrees in microelectronics science and engineering from Southern University of Science and Technology, Shenzhen, China, in 2020. He is currently working toward a Ph.D. degree at the same university. His research interests include high-speed optical receiver front-end circuits and wireline circuit design.

Zhengzhe Jia is an undergraduate student and is currently working toward a B.S degree at School of Microelectronics, Southern University of Science and Technology, Shenzhen, China. His research interests include high-speed optical receiver front-end circuits and CMOS analog-integrated circuits, including the CDR circuit.

Fuzhan Chen received a M.S. degree in microelectronics engineering from University of the Chinese Academy of Sciences, Beijing, China, in 2020. He is currently pursuing a Ph.D. degree in Electronics and Computer Engineering at Hong Kong University of Science and Technology under the joint Ph.D. training program in partnership with Southern University of Science and Technology. His research interests include high-speed optical communication and wireline IC design.

Xuewei Ding received the M.S. Degree in microelectronics engineering From Harbin Institute of Technology, Harbin, China, in 2007. He is currently working in ZTE.His reach interests include mix-signal design, high speed SerDes, both analog base & ADC base, high performance & high frequency PLL, etc.

C. Patrick Yue (SM’05–F’15) received a B.S. degree (Hons.) from the University of Texas at Austin, TX, USA, in 1992, and M.S. and Ph.D. degrees in electrical engineering from Stanford University, CA, USA, in 1994 and 1998, respectively. His research interest includes optical wireless physical layer circuits and systems, high-speed wireline communication SoC, millimeter-wave communication and sensing circuits, indoor positioning and image processing technologies for robotic applications, and edge computing accelerator design for IoT applications.

Corresponding author: Quan Pan, panq@sustech.edu.cn

DOI: 10.1088/1674-4926/43/7/072401

Abstract: This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz ?3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10^?12 BER at 26 Gb/s for a 2¹⁵?1 PRBS input with a ?7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.

Key words: clock and data recovery, equalizer, optical receiver, transimpedance amplifier, variable-gain amplifier

References

[1]	Chiang P C, Jiang J Y, Hung H W, et al. 4 × 25 Gb/s transceiver with optical front-end for 100 GbE system in 65 nm CMOS technology. IEEE J Solid State Circuits, 2015, 50, 573 doi: 10.1109/JSSC.2014.2365700
[2]	Chu S H, Bae W, Jeong G S, et al. A 22 to 26.5 Gb/s optical receiver with all-digital clock and data recovery in a 65 nm CMOS process. IEEE J Solid State Circuits, 2015, 50, 2603 doi: 10.1109/JSSC.2015.2465843
[3]	Rahman W, Yoo D, Liang J, et al. A 22.5-to-32-Gb/s 3.2-pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28-nm CMOS. IEEE J Solid State Circuits, 2017, 52, 3517 doi: 10.1109/JSSC.2017.2744661
[4]	Ozkaya I, Cevrero A, Francese P A, et al. A 60-Gb/s 1.9-pJ/bit NRZ optical receiver with low-latency digital CDR in 14-nm CMOS FinFET. IEEE J Solid State Circuits, 2018, 53, 1227 doi: 10.1109/JSSC.2017.2778286
[5]	Tsunoda Y, Shibasaki T, Oku H, et al. 25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs. Optical Fiber Communication Conference, 2015 doi: 10.1364/OFC.2015.Tu3G.4
[6]	Lee Y S, Ho W H, Chen W Z. A 25-Gb/s, 2.1-pJ/bit, fully integrated optical receiver with a baud-rate clock and data recovery. IEEE J Solid State Circuits, 2019, 54, 2243 doi: 10.1109/JSSC.2019.2907804
[7]	Han J, Choi B, Seo M, et al. A 20-Gb/s transformer-based current-mode optical receiver in 0.13-μm CMOS. IEEE Trans Circuits Syst II, 2010, 57, 348 doi: 10.1109/TCSII.2010.2047309
[8]	Komatsu Y, Shinmyo A, Kato S, et al. A 0.25–27-Gb/s PAM4/NRZ transceiver with adaptive power CDR and jitter analysis. IEEE J Solid State Circuits, 2019, 54, 2802 doi: 10.1109/JSSC.2019.2920082
[9]	Moayedi Pour Fard M, Liboiron-Ladouceur O, Cowan G E R. 1.23-pJ/bit 25-Gb/s inductor-less optical receiver with low-voltage silicon photodetector. IEEE J Solid State Circuits, 2018, 53, 1793 doi: 10.1109/JSSC.2018.2804042
[10]	Wu K C, Jri L. A 2 × 25Gb/s receiver with 2:5 DMUX for 100Gb/s Ethernet. IEEE J Solid-State Circuits, 2010, 45, 2421 doi: 10.1109/JSSC.2010.2074291
[11]	Wang Y P, Lu Y, Pan Q, et al. A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems. 2014 IEEE Radio Freq Integr Circuits Symp, 2014, 275
[12]	Pan Q, Wang Y P, Lu Y, et al. An 18-Gb/s fully integrated optical receiver with adaptive cascaded equalizer. IEEE J Sel Top Quantum Electron, 2016, 22, 361 doi: 10.1109/JSTQE.2016.2574567
[13]	Sun L, Pan Q, Wang K C, et al. A 26–28-Gb/s full-rate clock and data recovery circuit with embedded equalizer in 65-nm CMOS. IEEE Trans Circuits Syst I, 2014, 61, 2139 doi: 10.1109/TCSI.2014.2304669
[14]	Liu L X, Zou J, En Y F, et al. A high gain wide dynamic range transimpedance amplifier for optical receivers. J Semicond, 2014, 35, 015001 doi: 10.1088/1674-4926/35/1/015001
[15]	Dong Y, Martin K W. A 4-Gbps POF receiver using linear equalizer with multi-shunt-shunt feedbacks in 65-nm CMOS. IEEE Trans Circuits Syst II, 2013, 60, 617 doi: 10.1109/TCSII.2013.2273839
[16]	Pan Q, Luo X S. A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications. J Semicond, 2022, 43, 012401 doi: 10.1088/1674-4926/43/1/012401
[17]	Chen Y, Mak P I, Boon C C, et al. A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin. IEEE Trans Circuits Syst I, 2018, 65, 3014 doi: 10.1109/TCSI.2018.2829725
[18]	Chen Y, Mak P I, Boon C C, et al. A 27-Gb/s time-interleaved duobinary transmitter achieving 1.44-mW/Gb/s FOM in 65-nm CMOS. IEEE Microwave Wirel Compon Lett, 2017, 27, 839 doi: 10.1109/LMWC.2017.2735548
[19]	Zhao X T, Chen Y, Mak P I, et al. A 0.0018-mm² 153% locking-range CML-based divider-by-2 with tunable self-resonant frequency using an auxiliary negative-g_m cell. IEEE Trans Circuits Syst I, 2019, 66, 3330 doi: 10.1109/TCSI.2019.2925090
[20]	He J, Zhang Y G, Liu H, et al. A 56-Gb/s reconfigurable silicon-photonics transmitter using high-swing distributed driver and 2-tap in-segment feed-forward equalizer in 65-nm CMOS. IEEE Trans Circuits Syst I, 2022, 69, 1159 doi: 10.1109/TCSI.2021.3127723
[21]	Kong L S, Chen Y, Boon C C, et al. A wideband inductorless dB-linear automatic gain control amplifier using a single-branch negative exponential generator for wireline applications. IEEE Trans Circuits Syst I, 2018, 65, 3196 doi: 10.1109/TCSI.2018.2827065
[22]	Chen Y, Mak P, Yu H, et al. An area-efficient and tunable bandwidth- extension technique for a wideband CMOS amplifier handling 50+ Gb/s signaling. IEEE Trans Microwave Theory Tech, 2017, 65, 4960 doi: 10.1109/TMTT.2017.2720600
[23]	Wang J, Pan Q, Qin Y, et al. A fully integrated 25 Gb/s low-noise TIA+CDR optical receiver designed in 40-nm-CMOS. IEEE Trans Circuits Syst II, 2019, 66, 1698 doi: 10.1109/TCSII.2019.2925363
[24]	Zhao X T, Chen Y, Mak P I, et al. A 0.0285mm² 0.68pJ/bit single-loop full-rate bang-bang CDR without reference and separate frequency detector achieving an 8.2(Gb/s)/μs acquisition speed of PAM-4 data in 28nm CMOS. 2020 IEEE Custom Integrated Circuits Conference, 2020, 1 doi: 10.1109/CICC48029.2020.9075885
[25]	Zhao X T, Chen Y, Wang L, et al. A sub-0.25pJ/bit 47.6-to-58.8Gb/s reference-less FD-less single-loop PAM-4 Bang-Bang CDR with a deliberately-current-mismatch frequency acquisition technique in 28nm CMOS. 2021 IEEE Radio Frequency Integrated Circuits Symposium, 2021, 131 doi: 10.1109/RFIC51843.2021.9490486
[26]	Zhao X T, Chen Y, Mak P I, et al. A 0.14-to-0.29-pj/bit 14-GBaud/s trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit in 28-nm CMOS. IEEE Trans Circuits Syst I, 2021, 68, 89 doi: 10.1109/TCSI.2020.3038865
[27]	Balachandran A, Chen Y, Boon C C. A 32-Gb/s 3.53-mW/Gb/s adaptive receiver AFE employing a hybrid CTLE, edge-DFE and merged data-DFE/CDR in 65-nm CMOS. 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019, 221 doi: 10.1109/APCCAS47518.2019.8953146
[28]	Liao Q W, Zhang Y G, Ma S Y, et al. A 50-Gb/s PAM-4 silicon-photonic transmitter incorporating lumped-segment MZM, distributed CMOS driver, and integrated CDR. IEEE J Solid State Circuits, 2022, 57, 767 doi: 10.1109/JSSC.2021.3134874
[29]	Zhong M, Wang Q W, Chen Y, et al. A 4 × 25-Gb/s serializer with integrated CDR and 3-tap FFE driver for NIC optical interconnects. 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, 2021, 255 doi: 10.1109/ICTA53157.2021.9661798

Fig. 1. Optical receiver chipset architecture.

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Fig. 2. Optical receiver front-end.

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Fig. 3. (a) Schematic of the inverter-based TIA, (b) schematic of the TIA buffer, and (c) post-layout frequency response of TIA and buffer.

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Fig. 4. (Color online) (a) Schematic of the DOC and (b) its post-layout frequency response under different process corners.

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Fig. 5. (Color online) (a) Schematic of the high-BW gm-TIA VGA and (b) its post-layout frequency response of one nominal VGA under different process corners.

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Fig. 6. (Color online) (a) Normalized gain and bandwidth variations of the 3-stage VGA under different process corners and temperatures, and (b) simulated gain and bandwidth tuning range for different control words.

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Fig. 7. Reference-less 26-Gb/s CDR with built-in equalization.

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Fig. 8. (a) Schematic of the LC-VCO and (b) schematic of a single-stage delay cell with equalization.

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Fig. 9. (Color online) The CDR power breakdown.

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Fig. 10. (Color online) Chipset microphotograph.

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Fig. 11. Measured electrical frequency response of the optical front-end without 250-fF C_PD.

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Fig. 12. (Color online) Measured single-ended PRBS-15 eye diagram at optical front-end output for (a) 26 Gb/s and (b) 30 Gb/s.

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Fig. 13. (Color online) Measured single-ended PRBS-15 eye diagram for 26-Gb/s at chipset output.

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Fig. 14. (Color online) Measured differential eye diagram for 26-Gb/s PRBS-15: (a) without channel at chipset input, (b) without channel at chipset output, (c) with channel at chipset input, and (d) with channel at chipset output.

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Fig. 15. (Color online) The clock jitter of the recovered clock of the CDR output.

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Fig. 16. (Color online) Measured phase noise performance of the recovered CDR clock: (a) without attenuator and (b) with attenuator.

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Fig. 17. (Color online) Bathtub curves with and without the attenuator.

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Fig. 18. (Color online) Measured optical input sensitivity.

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Table 1. Control bits vs voltage and temperature variations at the output of the optical front-end.

Parameter	Default	Voltage variation		Temperature variation
Control bit	11100	11100	11111	11100	11000
Voltage supply (V)	1	0.9	0.9	1	1
Temperature (°C)	27	27	27	80	80
SNR (dB)	10.3	6.24	8.95	7.91	9.50
RMS jitter (ps)	2.37	3.50	3.10	2.69	2.29
Output (mV)	298	286	305	352	341

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Table 2. Comparison with published optical receivers/chipsets.

		Ref. [1]	Ref. [2]	Ref. [5]	Ref. [23]	This work
System	CMOS technology	65-nm	65-nm	130-nm BiCMOS	45-nm	65-nm
	Type	Chipset	Monolithic	Chipset	Monolithic	Chipset
	Supply voltage (V)	1.2	1/1.2	1.2	3.3/1.3	1/1.2
	Data rate (Gb/s)	25	26.5	25.78	25.78	26
	Sensitivity (10^?12 dBm)	?6.8	/	?8	/	?7.3
Front-End	PD responsivity (A/W)	0.47	/	/	0.5	0.4
	PD cap. (fF)	150	40^{^}	/	150	180^*
	Gain (dB?)	72.5	71	/	/	72
	BW (GHz)	21^##	20.4^#	/	/	20.4^##
	Power (mW)	68	35.8	<100	70	36
CDR	Rate type	Half	Half	Full	Half	Full
	Recovered clock PN(@1-MHz)	?98.3	/	/	/	?117.1
	Reference-less	Yes	No	/	Yes	Yes
	Clock jitter (ps)	1.01^**	1.28^**	/	/	0.955^**
	Power (mW)	120	218	100	100	104
^{^}Calculated value. ^80 fF is the PD capacitance itself. 100 fF is the on-chip PAD capacitance. ^*RMS jitter. ^#Simulated result with 40 fF. ^##Measured Result without C_PD.

DownLoad: CSV

[1]	Chiang P C, Jiang J Y, Hung H W, et al. 4 × 25 Gb/s transceiver with optical front-end for 100 GbE system in 65 nm CMOS technology. IEEE J Solid State Circuits, 2015, 50, 573 doi: 10.1109/JSSC.2014.2365700
[2]	Chu S H, Bae W, Jeong G S, et al. A 22 to 26.5 Gb/s optical receiver with all-digital clock and data recovery in a 65 nm CMOS process. IEEE J Solid State Circuits, 2015, 50, 2603 doi: 10.1109/JSSC.2015.2465843
[3]	Rahman W, Yoo D, Liang J, et al. A 22.5-to-32-Gb/s 3.2-pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28-nm CMOS. IEEE J Solid State Circuits, 2017, 52, 3517 doi: 10.1109/JSSC.2017.2744661
[4]	Ozkaya I, Cevrero A, Francese P A, et al. A 60-Gb/s 1.9-pJ/bit NRZ optical receiver with low-latency digital CDR in 14-nm CMOS FinFET. IEEE J Solid State Circuits, 2018, 53, 1227 doi: 10.1109/JSSC.2017.2778286
[5]	Tsunoda Y, Shibasaki T, Oku H, et al. 25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs. Optical Fiber Communication Conference, 2015 doi: 10.1364/OFC.2015.Tu3G.4
[6]	Lee Y S, Ho W H, Chen W Z. A 25-Gb/s, 2.1-pJ/bit, fully integrated optical receiver with a baud-rate clock and data recovery. IEEE J Solid State Circuits, 2019, 54, 2243 doi: 10.1109/JSSC.2019.2907804
[7]	Han J, Choi B, Seo M, et al. A 20-Gb/s transformer-based current-mode optical receiver in 0.13-μm CMOS. IEEE Trans Circuits Syst II, 2010, 57, 348 doi: 10.1109/TCSII.2010.2047309
[8]	Komatsu Y, Shinmyo A, Kato S, et al. A 0.25–27-Gb/s PAM4/NRZ transceiver with adaptive power CDR and jitter analysis. IEEE J Solid State Circuits, 2019, 54, 2802 doi: 10.1109/JSSC.2019.2920082
[9]	Moayedi Pour Fard M, Liboiron-Ladouceur O, Cowan G E R. 1.23-pJ/bit 25-Gb/s inductor-less optical receiver with low-voltage silicon photodetector. IEEE J Solid State Circuits, 2018, 53, 1793 doi: 10.1109/JSSC.2018.2804042
[10]	Wu K C, Jri L. A 2 × 25Gb/s receiver with 2:5 DMUX for 100Gb/s Ethernet. IEEE J Solid-State Circuits, 2010, 45, 2421 doi: 10.1109/JSSC.2010.2074291
[11]	Wang Y P, Lu Y, Pan Q, et al. A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems. 2014 IEEE Radio Freq Integr Circuits Symp, 2014, 275
[12]	Pan Q, Wang Y P, Lu Y, et al. An 18-Gb/s fully integrated optical receiver with adaptive cascaded equalizer. IEEE J Sel Top Quantum Electron, 2016, 22, 361 doi: 10.1109/JSTQE.2016.2574567
[13]	Sun L, Pan Q, Wang K C, et al. A 26–28-Gb/s full-rate clock and data recovery circuit with embedded equalizer in 65-nm CMOS. IEEE Trans Circuits Syst I, 2014, 61, 2139 doi: 10.1109/TCSI.2014.2304669
[14]	Liu L X, Zou J, En Y F, et al. A high gain wide dynamic range transimpedance amplifier for optical receivers. J Semicond, 2014, 35, 015001 doi: 10.1088/1674-4926/35/1/015001
[15]	Dong Y, Martin K W. A 4-Gbps POF receiver using linear equalizer with multi-shunt-shunt feedbacks in 65-nm CMOS. IEEE Trans Circuits Syst II, 2013, 60, 617 doi: 10.1109/TCSII.2013.2273839
[16]	Pan Q, Luo X S. A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications. J Semicond, 2022, 43, 012401 doi: 10.1088/1674-4926/43/1/012401
[17]	Chen Y, Mak P I, Boon C C, et al. A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin. IEEE Trans Circuits Syst I, 2018, 65, 3014 doi: 10.1109/TCSI.2018.2829725
[18]	Chen Y, Mak P I, Boon C C, et al. A 27-Gb/s time-interleaved duobinary transmitter achieving 1.44-mW/Gb/s FOM in 65-nm CMOS. IEEE Microwave Wirel Compon Lett, 2017, 27, 839 doi: 10.1109/LMWC.2017.2735548
[19]	Zhao X T, Chen Y, Mak P I, et al. A 0.0018-mm² 153% locking-range CML-based divider-by-2 with tunable self-resonant frequency using an auxiliary negative-g_m cell. IEEE Trans Circuits Syst I, 2019, 66, 3330 doi: 10.1109/TCSI.2019.2925090
[20]	He J, Zhang Y G, Liu H, et al. A 56-Gb/s reconfigurable silicon-photonics transmitter using high-swing distributed driver and 2-tap in-segment feed-forward equalizer in 65-nm CMOS. IEEE Trans Circuits Syst I, 2022, 69, 1159 doi: 10.1109/TCSI.2021.3127723
[21]	Kong L S, Chen Y, Boon C C, et al. A wideband inductorless dB-linear automatic gain control amplifier using a single-branch negative exponential generator for wireline applications. IEEE Trans Circuits Syst I, 2018, 65, 3196 doi: 10.1109/TCSI.2018.2827065
[22]	Chen Y, Mak P, Yu H, et al. An area-efficient and tunable bandwidth- extension technique for a wideband CMOS amplifier handling 50+ Gb/s signaling. IEEE Trans Microwave Theory Tech, 2017, 65, 4960 doi: 10.1109/TMTT.2017.2720600
[23]	Wang J, Pan Q, Qin Y, et al. A fully integrated 25 Gb/s low-noise TIA+CDR optical receiver designed in 40-nm-CMOS. IEEE Trans Circuits Syst II, 2019, 66, 1698 doi: 10.1109/TCSII.2019.2925363
[24]	Zhao X T, Chen Y, Mak P I, et al. A 0.0285mm² 0.68pJ/bit single-loop full-rate bang-bang CDR without reference and separate frequency detector achieving an 8.2(Gb/s)/μs acquisition speed of PAM-4 data in 28nm CMOS. 2020 IEEE Custom Integrated Circuits Conference, 2020, 1 doi: 10.1109/CICC48029.2020.9075885
[25]	Zhao X T, Chen Y, Wang L, et al. A sub-0.25pJ/bit 47.6-to-58.8Gb/s reference-less FD-less single-loop PAM-4 Bang-Bang CDR with a deliberately-current-mismatch frequency acquisition technique in 28nm CMOS. 2021 IEEE Radio Frequency Integrated Circuits Symposium, 2021, 131 doi: 10.1109/RFIC51843.2021.9490486
[26]	Zhao X T, Chen Y, Mak P I, et al. A 0.14-to-0.29-pj/bit 14-GBaud/s trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit in 28-nm CMOS. IEEE Trans Circuits Syst I, 2021, 68, 89 doi: 10.1109/TCSI.2020.3038865
[27]	Balachandran A, Chen Y, Boon C C. A 32-Gb/s 3.53-mW/Gb/s adaptive receiver AFE employing a hybrid CTLE, edge-DFE and merged data-DFE/CDR in 65-nm CMOS. 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019, 221 doi: 10.1109/APCCAS47518.2019.8953146
[28]	Liao Q W, Zhang Y G, Ma S Y, et al. A 50-Gb/s PAM-4 silicon-photonic transmitter incorporating lumped-segment MZM, distributed CMOS driver, and integrated CDR. IEEE J Solid State Circuits, 2022, 57, 767 doi: 10.1109/JSSC.2021.3134874
[29]	Zhong M, Wang Q W, Chen Y, et al. A 4 × 25-Gb/s serializer with integrated CDR and 3-tap FFE driver for NIC optical interconnects. 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, 2021, 255 doi: 10.1109/ICTA53157.2021.9661798

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Received: 28 January 2022 Revised: 15 March 2022 Online: Accepted Manuscript: 15 May 2022Uncorrected proof: 18 May 2022Published: 01 July 2022

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz ?3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10^?12 BER at 26 Gb/s for a 2¹⁵?1 PRBS input with a ?7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.

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A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

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A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

DOI: 10.1088/1674-4926/43/7/072401

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A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

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A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

DOI: 10.1088/1674-4926/43/7/072401

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