J. Semicond. > 2016, Volume 37?>?Issue 7?> 074004

SEMICONDUCTOR DEVICES

Advanced BCD technology with vertical DMOS based on a semi-insulation structure

Kui Ma, Xinghua Fu, Jiexin Lin and Fashun Yang

+ Author Affiliations

 Corresponding author: Yang Fashun Email: fashun@126.com

DOI: 10.1088/1674-4926/37/7/074004

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Abstract: A new semi-insulation structure in which one isolated island is connected to the substrate was proposed. Based on this semi-insulation structure, an advanced BCD technology which can integrate a vertical device without extra internal interconnection structure was presented. The manufacturing of the new semi-insulation structure employed multi-epitaxy and selectively multi-doping. Isolated islands are insulated with the substrate by reverse-biased PN junctions. Adjacent isolated islands are insulated by isolation wall or deep dielectric trenches. The proposed semi-insulation structure and devices fixed in it were simulated through two-dimensional numerical computer simulators. Based on the new BCD technology, a smart power integrated circuit was designed and fabricated. The simulated and tested results of Vertical DMOS, MOSFETs, BJTs, resistors and diodes indicated that the proposed semi-insulation structure is reasonable and the advanced BCD technology is validated.

Key words: semi-insulation structure, vertical DMOS, BCD technology, integrated circuit



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.  Cross-section of traditional BCD technology based on PN junction isolation structure.

.  Cross-section of the SOI-BCD technology.

.  The two-dimensional structure of the proposed BCD technology.

.  (Color online) The simulated result of the cross-section of the proposed semi-insulation structure.

.  Simulated results of the vertical DMOS. (a) Cross-section of vertical DMOS. (b) Simulated curve of $ {I_{{\rm{ds}}}} - {V_{{\rm{gs}}}} $. (c) Simulated curve of $ {I_{{\rm{ds}}}} - {V_{{\rm{ds}}}} $. (d) Simulated curve of D--S breakdown characteristic.

.  The cross-section of NMOS transistor.

.  The cross-section of NPN transistor.

.  Diagram of the smart power module chip.

.  SEM diagram of a trench in the proposed semi-insulation structure.

.  Tested breakdown characteristic curve of the semi-insulation structure.

.  Tested results of vertical DMOS. (a) Curve of $ {I_{{\rm{ds}}}} - {V_{{\rm{gs}}}} $. (b) Curve of $ {I_{{\rm{ds}}}} - {V_{{\rm{ds}}}} $.

.  Tested results of vertical NPN. (a) Curve of $ {I_{\rm{b}}} - {V_{{\rm{be}}}} $. (b) Curve of $ {I_{{\rm{ce}}}} - {V_{{\rm{ce}}}} $.

.  Tested results of NMOS. (a) Curve of $ {I_{{\rm{ds}}}} - {V_{{\rm{gs}}}} $. (b) Curve of $ {I_{{\rm{ds}}}} - {V_{{\rm{ds}}}} $$.

.   Tested results of other devices fabricated based on the proposed advanced BCD technology.
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    Received: 18 February 2016 Revised: 31 March 2016 Online: Published: 01 July 2016

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      Kui Ma, Xinghua Fu, Jiexin Lin, Fashun Yang. Advanced BCD technology with vertical DMOS based on a semi-insulation structure[J]. Journal of Semiconductors, 2016, 37(7): 074004. doi: 10.1088/1674-4926/37/7/074004 ****K Ma, X H Fu, J X Lin, F S Yang. Advanced BCD technology with vertical DMOS based on a semi-insulation structure[J]. J. Semicond., 2016, 37(7): 074004. doi: 10.1088/1674-4926/37/7/074004.
      Citation:
      Kui Ma, Xinghua Fu, Jiexin Lin, Fashun Yang. Advanced BCD technology with vertical DMOS based on a semi-insulation structure[J]. Journal of Semiconductors, 2016, 37(7): 074004. doi: 10.1088/1674-4926/37/7/074004 ****
      K Ma, X H Fu, J X Lin, F S Yang. Advanced BCD technology with vertical DMOS based on a semi-insulation structure[J]. J. Semicond., 2016, 37(7): 074004. doi: 10.1088/1674-4926/37/7/074004.

      Advanced BCD technology with vertical DMOS based on a semi-insulation structure

      DOI: 10.1088/1674-4926/37/7/074004

      • Department of Electronics, Guizhou University, Guiyang 550025, China

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      • Corresponding author: Yang Fashun Email: fashun@126.com
      • Received Date: 2016-02-18
      • Revised Date: 2016-03-31
      • Published Date: 2016-07-25

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