Abstract: A 1.4-2 GHz phase-locked loop (PLL) Σ-Δ fraction-N frequency synthesizer with automatic frequency control (AFC) for 802.11ah applications is presented. A class-C voltage control oscillator (VCO) ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order Σ-Δ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of ＜ -120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover,compared with the traditional class-A counterparts,the phase noise in class-C mode has been improved by 5 dB under the same power consumption.

Key words: phase-locked loop (PLL), class-C VCO, frequency synthesizer, low power, 802.11ah, transceiver