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J. Semicond. > 2015, Volume 36?>?Issue 9?> 095002

SEMICONDUCTOR INTEGRATED CIRCUITS

On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

Zhixiong Ren, Kefeng Zhang, Lanqi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu and Xuecheng Zou

+ Author Affiliations
DOI: 10.1088/1674-4926/36/9/095002

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Abstract: Three linear CMOS power amplifiers (PAs) with high output power (more than watt-level output power) for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer (PCT) and one 1.95 GHz PA using an on-chip series combining transformer (SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors (MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE.

Key words: CMOS, linearity, power combiner, transformers, power amplifier



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.  Comparison of watt-level output power CMOS PAs.

Figure 1.


.  Two types of power combining transformers. (a) PCT. (b) SCT.

Figure 2.


.  Layout of a PCT without power supply point.

Figure 3.


.  Layout of the improved PCT with power supply point.

Figure 4.


.  EM-simulated maximum available efficiency of the two PCTs.

Figure 5.


.  Layout of the proposed SCT.

Figure 6.


.  EM-simulated insertion loss of the SCT.

Figure 7.


.  Schematic diagram of the 2.4 GHz PA.

Figure 8.


.  Schematic diagram of the 1.95 GHz PA.

Figure 9.


.  Schematic of the 1.95 GHz power stage.

Figure 10.


.  Layout of the 2.4 GHz PAs. (a) PA1. (b) PA2.

Figure 11.


.  Bonding diagram of the 2.4 GHz PAs. (a) PA1. (b) PA2.

Figure 12.


.  Photograph of 2.4 GHz PAs test board. (a) PA1. (b) PA2.

Figure 13.


.  Measured $S$-parameters of the 2.4 GHz PAs.

Figure 14.


.  Measured power gain and PAE of the 2.4 GHz PAs.

Figure 15.


.  Measured intermodulation distortion in a two-tone test with 1 MHz tone spacing of the 2.4 GHz PA2.

Figure 16.


.  Layout of the designed 1.95 GHz PA.

Figure 17.


.  Maximum $S_{21}$ and the corresponding frequency versus gain control signal.

Figure 18.


.  Simulated $S_{11}$ and $S_{21}$ versus frequency.

Figure 19.


.  Simulated gains and PAEs in six power modes at 1.95 GHz.

Figure 20.


.  Simulated (a) ACPR and (b) AltCPR in six power modes at 1.95 GHz.

Figure 21.


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.   Summary of device sizes of the two 2.4 GHz PAs.

Table 1

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.   Summary of device sizes of the 1.95 GHz PA.

Table 2

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.   Performance comparison of watt-level 2.4 GHz linear CMOS Pas.

Table 3

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.   Performance comparison of linear CMOS Pas.

Table 4

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    Received: 03 March 2015 Revised: Online: Published: 01 September 2015

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      Zhixiong Ren, Kefeng Zhang, Lanqi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu, Xuecheng Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. Journal of Semiconductors, 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002 ****Z X Ren, K F Zhang, L Q Liu, C Li, X F Chen, D S Liu, Z L Liu, X C Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. J. Semicond., 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002.
      Citation:
      Zhixiong Ren, Kefeng Zhang, Lanqi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu, Xuecheng Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. Journal of Semiconductors, 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002 ****
      Z X Ren, K F Zhang, L Q Liu, C Li, X F Chen, D S Liu, Z L Liu, X C Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. J. Semicond., 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002.

      On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

      DOI: 10.1088/1674-4926/36/9/095002

      • School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China

      Funds:

      Project supported by the National Natural Science Foundation of China (No. 61076030).

      • Received Date: 2015-03-03
      • Accepted Date: 2015-04-15
      • Published Date: 2015-01-25

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