J. Semicond. > 2015, Volume 36?>?Issue 9?> 094002

SEMICONDUCTOR DEVICES

Design and fabrication of a 3.3 kV 4H-SiC MOSFET

Runhua Huang1, , Yonghong Tao2, Song Bai1, Gang Chen1, Ling Wang1, Ao Liu2, Neng Wei2, Yun Li1 and Zhifei Zhao1

+ Author Affiliations

 Corresponding author: Huang Runhua, huruhu@hotmail.com

DOI: 10.1088/1674-4926/36/9/094002

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Abstract: A 4H-SiC MOSFET with breakdown voltage higher than 3300 V has been successfully designed and fabricated. Numerical simulations have been performed to optimize the parameters of the drift layer and DMOSFET cell structure of active area. The n-type epilayer is 33μm thick with a doping of 2.5 × 1015 cm-3. The devices were fabricated with a floating guard ring edge termination. The drain current Id = 5 A at Vg = 20 V, corresponding to Vd = 2.5 V.

Key words: 4H-SiC, MOSFET, interface state



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Fig. 1.  Schematic device cross-sectional view of a 3300 V 4H-SiC MOSFET unit cell.

Fig. 2.  Drain current and electric field versus JFET width.

Fig. 3.  Drain family $I$-$V$ simulations of 4H-SiC DMOSFET.

Fig. 4.  Fabricated 3300 V 4H-SiC MOSFET.

Fig. 5.  Flow of self-aligned implantation technique with second mask defined by sidewall.

Fig. 6.  Transconductance characteristics of the 1200 V 4H-SiC MSOFET with active areas of 6.7 mm$^{2}$.

Fig. 7.  $I_{\rm D}$-$V_{\rm D}$ characteristics of the 3300 V 4H-SiC MSOFET (active area $=$ 0.6 mm$^{2})$.

Fig. 8.  $I_{\rm D}$-$V_{\rm D}$ characteristics of the 3300 V 4H-SiC MSOFET (active area $=$ 6.7 mm$^{2})$.

Fig. 9.  Blocking characteristics of the 6.7 mm$^{2}$ 3300 V MOSFET at $V_{\rm gs}$ $=$ 0 V.

Table 1.   Flow of self-aligned implantation technique with second mask defined by sidewall.

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    Received: 16 October 2014 Revised: Online: Published: 01 September 2015

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      Runhua Huang, Yonghong Tao, Song Bai, Gang Chen, Ling Wang, Ao Liu, Neng Wei, Yun Li, Zhifei Zhao. Design and fabrication of a 3.3 kV 4H-SiC MOSFET[J]. Journal of Semiconductors, 2015, 36(9): 094002. doi: 10.1088/1674-4926/36/9/094002 ****R H Huang, Y H Tao, S Bai, G Chen, L Wang, A Liu, N Wei, Y Li, Z F Zhao. Design and fabrication of a 3.3 kV 4H-SiC MOSFET[J]. J. Semicond., 2015, 36(9): 094002. doi: 10.1088/1674-4926/36/9/094002.
      Citation:
      Runhua Huang, Yonghong Tao, Song Bai, Gang Chen, Ling Wang, Ao Liu, Neng Wei, Yun Li, Zhifei Zhao. Design and fabrication of a 3.3 kV 4H-SiC MOSFET[J]. Journal of Semiconductors, 2015, 36(9): 094002. doi: 10.1088/1674-4926/36/9/094002 ****
      R H Huang, Y H Tao, S Bai, G Chen, L Wang, A Liu, N Wei, Y Li, Z F Zhao. Design and fabrication of a 3.3 kV 4H-SiC MOSFET[J]. J. Semicond., 2015, 36(9): 094002. doi: 10.1088/1674-4926/36/9/094002.

      Design and fabrication of a 3.3 kV 4H-SiC MOSFET

      DOI: 10.1088/1674-4926/36/9/094002
      • 1.

        Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing 210016, China

      • 2.

        Nanjing Electronic Devices Institute, Nanjing 210016, China

      Funds:

      Project supported by the National High Technology Research and Development Program of China (No. 2014AA052401).

      More Information
      • Corresponding author: Huang Runhua, huruhu@hotmail.com
      • Received Date: 2014-10-16
      • Accepted Date: 2015-04-19
      • Published Date: 2015-01-25

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