Eliminating the floating-body effects in a novel CMOS-compatible thin-SOI LDMOS

Yongheng Jiang; Xiaorong Luo; Yanfei Li; Pei Wang; Ye Fan; Kun Zhou; Qi Wang; Xiarong Hu; Bo Zhang

doi:10.1088/1674-4926/34/9/094005

J. Semicond. > 2013, Volume 34?>?Issue 9?> 094005

SEMICONDUCTOR DEVICES

Eliminating the floating-body effects in a novel CMOS-compatible thin-SOI LDMOS

Yongheng Jiang, Xiaorong Luo, Yanfei Li, Pei Wang, Ye Fan, Kun Zhou, Qi Wang, Xiarong Hu and Bo Zhang

+ Author Affiliations

Corresponding author: Luo Xiaorong, Email:xrluo@uestc.edu.cn

DOI: 10.1088/1674-4926/34/9/094005

Abstract: A novel CMOS-compatible thin film SOI LDMOS with a novel body contact structure is proposed. It has a Si window and a P-body extended to the substrate through the Si window, thus, the P-body touches the P⁺ region to form the body contact. Compared with the conventional floating body SOI LDMOS (FB SOI LDMOS) structure, the new structure increases the off-state BV by 54%, decreases the specific on resistance by 20%, improves the output characteristics significantly, and suppresses the self-heating effect. Furthermore, the advantages of the low leakage current and low output capacitance of SOI devices do not degrade.

Key words: thin film SOI LDMOS, body contact, floating body effect, parasitic BJT effect

References

[1]	Colinge J P. Silicon-on-insulator technology:materials to VLSI, 2nd ed. Netherlands:Kluwer Academic Publisher, 1997:123
[2]	Xue S B, Huang R, Huang D T, et al. Impact of the displacement damage in channel and source/drain regions on the DC characteristics degradation in deep-submicron MOSFETs after heavy ion irradiation. Chin Phys B, 2010, 19(11):117307 doi: 10.1088/1674-1056/19/11/117307
[3]	Choi J Y, Fossum J G. Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's. IEEE Trans Electron Devices, 1991, 38(6):1384 doi: 10.1109/16.81630
[4]	Eric P Ver P, Cuong T N, Simon W S, et al. Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's. IEEE Trans Electron Devices, 1994, 41(6):970 doi: 10.1109/16.293310
[5]	Chen C E D, Mishel M, Sundaresan R, et al. Single-transistor latch in SOI MOSFET's. IEEE Electron Device Lett, 1988, 9(12):636 doi: 10.1109/55.20420
[6]	Liu Y L, Liu X Y, Han Z S, et al. Simulation of a novel Schottky body-contacted structure suppressing floating body effect in partially-depleted SOI nMOSFET's. Chinese Journal of Semiconductors, 2002, 23(10):1019
[7]	Cheng X H, Yang W W, Song Z R, et al. A novel LDMOS structure in thin film patterned-SOI technology with a silicon window beneath p well. Chinese Journal of Semiconductors, 2004, 25(12):1581
[8]	Sleight J, Mistry K. A compact Schottky body contact technology for SOI transistors. International Electron Devices Meeting, Washington, DC, USA, 1997:419
[9]	Min B W, Wu L K D, Caffo D, et al. Reduction of hysterestic propagation delay with less performance degradation by novel body contact in PD SOI application. IEEE International SOI Conference, Williamsburg, USA, 2002:169
[10]	Zhou J H, Gao M H, Pang S K, et al. Body-contact self-bias effect in partially depleted SOI-CMOS and alternatives to suppress floating body effect. Journal of Semiconductors, 2011, 32(2):024003 doi: 10.1088/1674-4926/32/2/024003
[11]	Liu Y L, Liu X Y, Han Z S, et al. Floating body effect in partially depleted SOI nMOSFET with asymmetric structure and Ge-implantation. Chinese Journal of Semiconductors, 2002, 23(11):1154
[12]	Cai X W, Hai C H. Study of body contact of partial depleted SOI NMOS devices. 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 2006:212
[13]	Hai C H, Han Z S, Zhao L X, et al. Study of improved performance of SOI devices and circuits. Chinese Journal of Semiconductors, 2006, 27:322
[14]	Daghighi A, Osman M A. Three-dimensional simulation of body contact structures in PD SOI MOSFETs. Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium, Boise, USA, 2003:288
[15]	Merchant S, Arnold E, Baumgart S, et al. Realization of high breakdown voltage (> 700 V) in thin SOI devices. Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, Baltimore, USA, 1991:31
[16]	Baliga B J. Power semiconductor devices. Boston:MA PWS, 1996:155
[17]	Bi J S, Song L M, Hai C H, et al. Back-gate effect of SOI LDMOSFETs. Journal of Semiconductors, 2008, 29(11):2148 http://www.hi0543.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=08032508&flag=1

Fig. 1. Schematic cross sections of (a) the proposed SOI LDMOS in a PIC and (b) the FB SOI LDMOS, with various current components marked

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Fig. 2. Equipotential contours (10 V/contour) of (a) proposed LDMOS at $C_{\rm G}$ = 2.2 × 10$^{20}$ cm$^{-4}$ (BV = 210 V), and the FB LDMOS at (b) $C_{\rm G}$ = 2.2 × 10$^{20}$ cm$^{-4}$ (BV = 41.8 V) and (c) $C_{\rm G}$ = 1.4 × 10$^{20}$ cm$^{-4}$ (BV = 136.3 V)

DownLoad: Full-Size Img PowerPoint

Fig. 3. (a) Influences of $C_{\rm G}$ on the $I_{\rm LDS}$-$V_{\rm DS}$ characteristics in the off-state. (b) Lateral electric field distributions of the FB SOI LDMOS ($V_{\rm DS}$ = BV = 41.8 V at $C_{\rm G}$ = 2.2 × 10$^{20}$ cm$^{-4})$

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Fig. 4. (a) $I_{\rm DS}$-$V_{\rm DS}$ characteristics with $V_{\rm GS}$ -$V_{\rm TH}$ = 1 V, 3 V, and 5 V. (b) $I_{\rm DS}$-$V_{\rm DS}$ and $I_{\rm HOLE}$-$V_{\rm DS}$ characteristics of FB SOI LDMOS at $V_{\rm GS}$ -$V_{\rm TH}$ = 3 V (The inset indicates the $I_{\rm DS}$-$V_{\rm DS}$ characteristics in low $V_{\rm DS})$. (c) Parameters extracted from (b). (At $C_{\rm G}$ = 2.2 × 10$^{20}$ cm$^{-4})$

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Fig. 5. Influences of $W_{\rm S}$ on (a) BV (on-state $V_{\rm GS}$ -$V_{\rm TH}$ = 3 V) (b) $V_{\rm th}$ and $T_{\rm max}$. ($C_{\rm G}$ = 2.2 × 10$^{20}$ cm$^{-4}$, $N_{\rm ch}$ = 1.7 × 10$^{17}$ cm$^{-3})$

DownLoad: Full-Size Img PowerPoint

Fig. 6. Dependences of BV and $R_{\rm on, \, sp}$ on $C_{\rm G}$

DownLoad: Full-Size Img PowerPoint

Fig. 7. Influences of $N_{\rm ch}$ on $V_{\rm th}$ and BV ($C_{\rm G}$ = 2.2 × 10$^{20}$ cm$^{-4}$ for proposed SOI, $C_{\rm G}$ = 1.4 × 10$^{20}$ cm$^{-4}$ for FB SOI)

DownLoad: Full-Size Img PowerPoint

[1]	Colinge J P. Silicon-on-insulator technology:materials to VLSI, 2nd ed. Netherlands:Kluwer Academic Publisher, 1997:123
[2]	Xue S B, Huang R, Huang D T, et al. Impact of the displacement damage in channel and source/drain regions on the DC characteristics degradation in deep-submicron MOSFETs after heavy ion irradiation. Chin Phys B, 2010, 19(11):117307 doi: 10.1088/1674-1056/19/11/117307
[3]	Choi J Y, Fossum J G. Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's. IEEE Trans Electron Devices, 1991, 38(6):1384 doi: 10.1109/16.81630
[4]	Eric P Ver P, Cuong T N, Simon W S, et al. Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's. IEEE Trans Electron Devices, 1994, 41(6):970 doi: 10.1109/16.293310
[5]	Chen C E D, Mishel M, Sundaresan R, et al. Single-transistor latch in SOI MOSFET's. IEEE Electron Device Lett, 1988, 9(12):636 doi: 10.1109/55.20420
[6]	Liu Y L, Liu X Y, Han Z S, et al. Simulation of a novel Schottky body-contacted structure suppressing floating body effect in partially-depleted SOI nMOSFET's. Chinese Journal of Semiconductors, 2002, 23(10):1019
[7]	Cheng X H, Yang W W, Song Z R, et al. A novel LDMOS structure in thin film patterned-SOI technology with a silicon window beneath p well. Chinese Journal of Semiconductors, 2004, 25(12):1581
[8]	Sleight J, Mistry K. A compact Schottky body contact technology for SOI transistors. International Electron Devices Meeting, Washington, DC, USA, 1997:419
[9]	Min B W, Wu L K D, Caffo D, et al. Reduction of hysterestic propagation delay with less performance degradation by novel body contact in PD SOI application. IEEE International SOI Conference, Williamsburg, USA, 2002:169
[10]	Zhou J H, Gao M H, Pang S K, et al. Body-contact self-bias effect in partially depleted SOI-CMOS and alternatives to suppress floating body effect. Journal of Semiconductors, 2011, 32(2):024003 doi: 10.1088/1674-4926/32/2/024003
[11]	Liu Y L, Liu X Y, Han Z S, et al. Floating body effect in partially depleted SOI nMOSFET with asymmetric structure and Ge-implantation. Chinese Journal of Semiconductors, 2002, 23(11):1154
[12]	Cai X W, Hai C H. Study of body contact of partial depleted SOI NMOS devices. 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 2006:212
[13]	Hai C H, Han Z S, Zhao L X, et al. Study of improved performance of SOI devices and circuits. Chinese Journal of Semiconductors, 2006, 27:322
[14]	Daghighi A, Osman M A. Three-dimensional simulation of body contact structures in PD SOI MOSFETs. Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium, Boise, USA, 2003:288
[15]	Merchant S, Arnold E, Baumgart S, et al. Realization of high breakdown voltage (> 700 V) in thin SOI devices. Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, Baltimore, USA, 1991:31
[16]	Baliga B J. Power semiconductor devices. Boston:MA PWS, 1996:155
[17]	Bi J S, Song L M, Hai C H, et al. Back-gate effect of SOI LDMOSFETs. Journal of Semiconductors, 2008, 29(11):2148 http://www.hi0543.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=08032508&flag=1

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Received: 22 January 2013 Revised: 15 April 2013 Online: Published: 01 September 2013

A novel CMOS-compatible thin film SOI LDMOS with a novel body contact structure is proposed. It has a Si window and a P-body extended to the substrate through the Si window, thus, the P-body touches the P⁺ region to form the body contact. Compared with the conventional floating body SOI LDMOS (FB SOI LDMOS) structure, the new structure increases the off-state BV by 54%, decreases the specific on resistance by 20%, improves the output characteristics significantly, and suppresses the self-heating effect. Furthermore, the advantages of the low leakage current and low output capacitance of SOI devices do not degrade.

Eliminating the floating-body effects in a novel CMOS-compatible thin-SOI LDMOS

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