Abstract: A new electrostatic discharge (ESD) protection circuit based on a standard 0.6μm CMOS p-well process is designed according to the whole-chip ESD protection theory and verified by a multi-project wafer (MPW) fabrication.The characteristics of the new ESD protection structure and traditional gate grounded nMOS (GG-nMOS) protection circuit with the same channel ratio of width/length in the MPW are measured by a transmission line pulse generator system.The results show that the area of the new ESD protection circuit decreases about 30%.Lower static current and an increase in the failure voltage up to 30% are achieved compared to those of a GG-nMOS protection circuit with the same manufacturing process.An ESD failure voltage up to 5kV under human-body mode test conditions is obtained.

Key words: electrostatic discharge, protection circuit, transmission line pulse, human-body mode