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J. Semicond. > 2008, Volume 29?>?Issue 4?> 713-718

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Design and Implementation of an FDP Chip

Chen Liguang, Wang Yabin, Wu Fang, Lai Jinmei, Tong Jiarong, Zhang Huowen, Tu Rui, Wang Jian, Wang Yuan, Shen Qiushi, Yu Hui, Huang Junnai, Lu Haizhou and Pan Guanghua

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Abstract: A novel Fudan programmable logic chip (FDP) was designed and implemented with a SMIC 0.18μm CMOS logic process.The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT.The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly.The FDP contains 1,600 programmable logic cells,160 programmable I/O,and 16kbit dual port block RAM.Its die size is 6.104mm×6.620mm,with the package of QFP208.The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.

Key words: FPGA, programmable logic block, programmable routing resource, switch box

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    Received: 18 August 2015 Revised: 01 November 2007 Online: Published: 01 April 2008

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      Chen Liguang, Wang Yabin, Wu Fang, Lai Jinmei, Tong Jiarong, Zhang Huowen, Tu Rui, Wang Jian, Wang Yuan, Shen Qiushi, Yu Hui, Huang Junnai, Lu Haizhou, Pan Guanghua. Design and Implementation of an FDP Chip[J]. Journal of Semiconductors, 2008, 29(4): 713-718. ****Chen L G, Wang Y B, Wu F, Lai J M, Tong J R, Zhang H W, Tu R, Wang J, Wang Y, Shen Q S, Yu H, Huang J N, Lu H Z, Pan G H. Design and Implementation of an FDP Chip[J]. J. Semicond., 2008, 29(4): 713.
      Citation:
      Chen Liguang, Wang Yabin, Wu Fang, Lai Jinmei, Tong Jiarong, Zhang Huowen, Tu Rui, Wang Jian, Wang Yuan, Shen Qiushi, Yu Hui, Huang Junnai, Lu Haizhou, Pan Guanghua. Design and Implementation of an FDP Chip[J]. Journal of Semiconductors, 2008, 29(4): 713-718. ****
      Chen L G, Wang Y B, Wu F, Lai J M, Tong J R, Zhang H W, Tu R, Wang J, Wang Y, Shen Q S, Yu H, Huang J N, Lu H Z, Pan G H. Design and Implementation of an FDP Chip[J]. J. Semicond., 2008, 29(4): 713.

      Design and Implementation of an FDP Chip

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      • ASIC and System State Key Laboratory,Fudan University,Shanghai 200433,China

      Funds:

      國(guó)家高技術(shù)研究發(fā)展計(jì)劃（863計(jì)劃）

      國(guó)家自然科學(xué)基金

      • Received Date: 2015-08-18
      • Accepted Date: 2007-09-27
      • Revised Date: 2007-11-01
      • Published Date: 2008-04-03

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