Abstract: A 2.5Gb/s/ch data recovery (DR) circuit is designed for an SFI-5 interface.To make the parallel data bit-synchronization and reduce the bit error rate (BER),a delay locked loop (DLL) is used to place the center of the data eye exactly at the rising edge of the data-sampling clock.A single channel DR circuit was fabricated in TSMC’s standard 0.18μm CMOS process.The chip area is 0.46mm2.With a 2³¹-1 pseudorandom bit sequence (PRBS) input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps.The sensitivity of the single channel DR is less than 20mV with 1e12 BER.

Key words: data recovery, delay locked loop, bit-synchronization