Abstract: This paper describes the design of a low voltage differential signal (LVDS) transmitter and receiver with high speed and low power for CPU,LCD,FPGA,and other fast links.In the proposed transmitter,a stable reference and a common mode feedback circuit are integrated into the LVDS drivers,which enable the transmitter to tolerate variations of process,temperature,and supply voltage.The proposed receiver implements a rail-to-rail amplifier architecture that allows a 1.6Gb/s transmission.The transmitter and receiver are implemented in HJ TC 3.3V,0.18μm CMOS technology.The experimental results demonstrate that the transmitter and receiver reach 1.6Gb/s.The transmitter and receiver pad cells exhibit a power consumption of 35 and 6mW,respectively.

Key words: LVDS, rail to rail, low power