Abstract: Several key techniques for a PLL-type frequency synthesizer for WLAN receivers are studied.Its structure is analyzed and the main parameters are proposed.A monolithic LC-tuned voltage controlled oscillator (LC-VCO) with low phase noise is fabricated with TSMC 0.18μm RF (radio frequency) CMOS technology.The measured phase noise is -117dBc/Hz at 4MHz off the center frequency of 4.189GHz.A down-scaling circuit with low power dissipation was fabricated in a TSMC 0.18μm mixed-signal CMOS process.The measured results show that the IC can work well under a 1.8V power supply.Its total power dissipation is only 13mW.

Key words: PLL, WLAN, VCO, down scaling