Abstract: A USB 2.0 high speed transceiver was designed in 0.13μm mixed-signal CMOS technology.A high-speed current-mode differential comparator,a phase detector with window-enabling logic,and an analog continuously-adjusting CMFB were developed to meet the specifications and 0.13μm technology.The transceiver has been fabricated in SMIC.The transmitter jitter was 53ps,and the bit error rate of the receiver was less than 1e-12.The power consumption was 42.5mW at a power supply of 1.2V, and the chip area was 900μm×700μm.

Key words: differential envelope detector, phase locked loop, loop filter, common mode feedback