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Abstract: A conversion-precision and sampling-rate programmable pipeline analog-to-digital converter (ADC),without adjusting the bias current of operational amplifiers,is presented in this paper.This ADC achieves a conversion-precision of 8 to 11bits and a sampling-rate from 400k to 40MSa/s.To increase the power-on speed and reduce the power consumption,a novel pre-charged switched operational amplifier is proposed.The power can be significantly reduced by adopting an improved current modulated power scaling (CMPS) technique,the proposed switched operational amplifier,a SHA-less technique,and a dynamic comparator.The ADC is designed in a 1.8V 1P6M 0.18μm CMOS process.Simulation results indicate that the ADC exhibits a spurious free dynamic range (SFDR) of 81dB and a signal-to-noise and distortion ratio (SNDR) of 67dB.Programmed at 11bits and 40MSa/s,the ADC consumes 29mW when a 19.02MHz sine signal is fed-in.
Key words: pipeline, ADC, switched operational amplifier
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Received: 18 August 2015 Revised: 04 December 2007 Online: Published: 01 May 2008
| Citation: |
Wei Qi, Yin Xiumei, Yang Bin, Yang Huazhong. A Novel Sampling Precision and Rate Programmable Pipeline ADCwith Improved Current Modulated Power Scaling[J]. Journal of Semiconductors, 2008, 29(5): 1010-1015.
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Wei Q, Yin X M, Yang B, Yang H Z. A Novel Sampling Precision and Rate Programmable Pipeline ADCwith Improved Current Modulated Power Scaling[J]. J. Semicond., 2008, 29(5): 1010.
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