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J. Semicond. > 2021, Volume 42?>?Issue 6?> 062803

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A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

Jongwoon Yoon and Kwangsoo Kim

+ Author Affiliations + Find other works by these authors

• Department of Electronic Engineering, Sogang University, Seoul 04107, KoreaDepartment of Electronic Engineering, Sogang University, Seoul 04107, Korea

Author Bio:

• Jongwoon Yoon got his BS degree from Sogang University in 2020. Now he is in Master's course at Sogang University under the supervision of Prof. Kim. His research focuses on 4H-SiC MOSFET.
• Kwangsoo Kim received his BS degree in 1981, MS degree in 1983, and PhD at Sogang University in 1992. Since then, he joined Electronics and Telecommunications Research Institute (ETRI), Institute for Information Technology Advancement (IITA) and Daegu Gyeongbuk Institute of Science and Technology (DGIST). In 2008, he joined Sogang University as a full professor. His research focuses on 4H-SiC semiconductor devices and process.

• Jongwoon Yoon
• Kwangsoo Kim

 Corresponding author: Kwangsoo Kim, kimks@sogang.ac.kr

DOI: 10.1088/1674-4926/42/6/062803

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Abstract: A split gate MOSFET (SG-MOSFET) is widely known for reducing the reverse transfer capacitance (C_RSS). In a 3.3 kV class, the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field. In addition to the poor static performance, the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering (DIBL) caused by the high gate oxide electric field. As such, a 3.3 kV 4H-SiC split gate MOSFET with a grounded central implant region (SG-CIMOSFET) is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance. The SG-CIMOSFET has a significantly low on-resistance (R_ON) and maximum gate oxide field (E_OX) due to the central implant region. A grounded central implant region significantly reduces the C_RSS and gate drain charge (Q_GD) by partially screening the gate-to-drain capacitive coupling. Compared to a planar MOSFET, the SG MOSFET, central implant MOSFET (CIMOSFET), the SG-CIMOSFET improve the R_ON×Q_GD by 83.7%, 72.4% and 44.5%, respectively. The results show that the device features not only the smallest switching energy loss but also the fastest switching time.

Key words: 4H-SiC, split gate, on-resistance, reverse transfer capacitance, switching energy loss, switching time

References

[1]	Baliga B J. Power MOSFETs Fundamentals of power semiconductor devices. Boston, MA: Springer US, 2008, 276
[2]	Ji S Q, Zhang Z Y, Wang F. Overview of high voltage sic power semiconductor devices: Development and application. CES Trans Electr Mach Syst, 2017, 1, 254 doi: 10.23919/TEMS.2017.8086104
[3]	Cooper J A, Agarwal A. SiC power-switching devices-the second electronics revolution. Proc IEEE, 2002, 90, 956 doi: 10.1109/JPROC.2002.1021561
[4]	Wang G Y, Wang F, Magai G R, et al. Performance comparison of 1200V 100A SiC MOSFET and 1200V 100A silicon IGBT. 2013 IEEE Energy Convers Congr Expo, 2013, 3230
[5]	Nakamura T, Nakano Y, Aketa M, et al. High performance SiC trench devices with ultra-low Ron. 2011 International Electron Devices Meeting, 2011, 26.5.1
[6]	Sampath M, Morisette D T, Cooper J A. Comparison of single- and double-trench UMOSFETs in 4H-SiC. Mater Sci Forum, 2018, 924, 752 doi: 10.4028/www.scientific.net/MSF.924.752
[7]	Krishnaswami S, Das M, Hull B, et al. Gate oxide reliability of 4H-SiC MOS devices. 2005 IEEE International Reliability Physics Symposium, 2005, 592
[8]	Xu S M, Ren C H, Liang Y C, et al. Theoretical analysis and experimental characterization of the dummy-gated VDMOSFET. IEEE Trans Electron Devices, 2001, 48, 2168 doi: 10.1109/16.944212
[9]	Agarwal A, Han K, Baliga B J. 2.3 kV 4H-SiC accumulation-channel split-gate planar power MOSFETs with reduced gate charge. IEEE J Electron Devices Soc, 2020, 8, 499 doi: 10.1109/JEDS.2020.2991355
[10]	Han K, Baliga B J, Sung W. A novel 1.2 kV 4H-SiC buffered-gate (BG) MOSFET: Analysis and experimental results. IEEE Electron Device Lett, 2018, 39, 248 doi: 10.1109/LED.2017.2785771
[11]	Vudumula P, Kotamraju S. Design and optimization of 1.2-kV SiC planar inversion MOSFET using split dummy gate concept for high-frequency applications. IEEE Trans Electron Devices, 2019, 66, 5266 doi: 10.1109/TED.2019.2949459
[12]	Zhang Q C J, Duc J, Hull B, et al. CIMOSFET: A new MOSFET on SiC with a superior Ron·Qgd figure of merit. Mater Sci Forum, 2015, 821–823, 765
[13]	Zhang Q J, Wang G Y, Doan H, et al. Latest results on 1200 V 4H-SiC CIMOSFETs with Rsp, on of 3.9 mΩ·cm2 at 150 °C. 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2015, 89
[14]	TCAD Sentaurus Device Manual, Synopsys. 2016, Inc., Mountain View, CA, USA
[15]	Darwish M N, Lentz J L, Pinto M R, et al. An improved electron and hole mobility model for general purpose device simulation. IEEE Trans Electron Devices, 1997, 44, 1529 doi: 10.1109/16.622611
[16]	Mujtaba S A. Advanced mobility models for design and simulation of deep submicrometer MOSFETs. PhD Dissertation, Stanford University, 1995
[17]	Han K, Baliga B J, Sung W. Split-gate 1.2-kV 4H-SiC MOSFET: Analysis and experimental validation. IEEE Electron Device Lett, 2017, 38, 1437 doi: 10.1109/LED.2017.2738616
[18]	Wei J, Zhang M, Jiang H P, et al. Low ON-resistance SiC trench/planar MOSFET with reduced OFF-state oxide field and low gate charges. IEEE Electron Device Lett, 2016, 37, 1458 doi: 10.1109/LED.2016.2609599
[19]	Wei J, Zhang M, Jiang H P, et al. Dynamic degradation in SiC trench MOSFET with a floating p-shield revealed with numerical simulations. IEEE Trans Electron Devices, 2017, 64, 2592 doi: 10.1109/TED.2017.2697763
[20]	Ren M, Chen Z, Niu B, et al. A low miller capacitance VDMOS with shield gate and oxide trench. 2016 IEEE International Nanoelectronics Conference (INEC), 2016, 1
[21]	Basler T, Heer D, Peters D, et al. Practical aspects and body diode robustness of a 1200 V SiC trench MOSFET. International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2018, 1
[22]	Maerz A, Bertelshofer T, Bakran M, et al. A novel gate drive concept to eliminate parasitic turn-on of SiC MOSFET in low inductance power modules. International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2017, 1
[23]	Tian K, Hallén A, Qi J W, et al. An improved 4H-SiC trench-gate MOSFET with low ON-resistance and switching loss. IEEE Trans Electron Devices, 2019, 66, 2307 doi: 10.1109/TED.2019.2905636
[24]	Morikawa T, Ishigaki T, Shima A. Device design consideration for robust SiC VDMOSFET with self-aligned channels formed by tilted implantation. IEEE Trans Electron Devices, 2019, 66, 3447 doi: 10.1109/TED.2019.2924969
[25]	Zhou X T, Yue R F, Zhang J, et al. 4H-SiC trench MOSFET with floating/grounded junction barrier-controlled gate structure. IEEE Trans Electron Devices, 2017, 64, 4568 doi: 10.1109/TED.2017.2755721

Fig. 1.  (Color online) Schematic cross-sectional views of the MOSFETs. (a) Planar MOSFET. (b) SG-MOSFET. (c) CIMOSFET. (d) SG-CIMOSFET.

DownLoad: Full-Size Img PowerPoint

Fig. 2.  (Color online) (a) E_OX and R_ON changes of the planar MOSFET according to the W_JFET, and (b) influence of the L_split on BV, R_ON, Q_GD and E_OX in SG-MOSFET. BV is extracted at V_GS = 0 V and I_DS = 1 μA/cm².

DownLoad: Full-Size Img PowerPoint

Fig. 3.  (Color online) Electron current density distribution when breakdown occurs in the SG-MOSFET (a) when L_split = 0.5 μm, and (b) when L_split = 0.6 μm.

DownLoad: Full-Size Img PowerPoint

Fig. 4.  (Color online) (a) R_ON and BV relation in the SG-CIMOSFET according to change in W_P and H_P. (b)–(d) Impact ionization position when breakdown occurs in the SG-CIMOSFET according to change in W_P and H_P (the arrow indicates the breakdown point).

DownLoad: Full-Size Img PowerPoint

Fig. 5.  (a) E_OX changes and (b) Q_GD changes in the SG-CIMOSFET according to change in W_P and H_P. E_OX is obtained at V_DS = 3000 V and V_GS = 0 V.

DownLoad: Full-Size Img PowerPoint

Fig. 6.  The I–V characteristics of the four devices. R_ON and saturation current is obtained for V_GS = 20 V. BV is extracted at V_GS = 0 V and I_DS = 1 μA/cm².

DownLoad: Full-Size Img PowerPoint

Fig. 7.  (Color online) Off-state electric field distributions of the four devices when V_GS = 0 V and V_DS = 3000 V.

DownLoad: Full-Size Img PowerPoint

Fig. 8.  (Color online) The band diagram in the channel of the four devices at V_DS = 0 V, V_DS = 3000 V in off-state.

DownLoad: Full-Size Img PowerPoint

Fig. 9.  (Color online) (a) Reverse transfer capacitance characteristics (C_RSS) of the five devices. (b) Input capacitance (C_ISS) and drain source capacitance (C_DS) characteristics of the five devices (when V_GS = 0 V, AC signal of 1 MHz).

DownLoad: Full-Size Img PowerPoint

Fig. 10.  (Color online) (a) Depletion lines and reverse transfer capacitance models of the five devices when V_DS = 0 V, V_GS = 0 V. (b) Depletion lines of the five devices when V_DS = 800 V, V_GS = 0 V. The solid black line represents the depletion layer.

DownLoad: Full-Size Img PowerPoint

Fig. 11.  Gate charge characteristics and test circuit of the four devices.

DownLoad: Full-Size Img PowerPoint

Fig. 12.  Switching waveforms of the four devices. The active areas of all DUT are set to 1 cm².

DownLoad: Full-Size Img PowerPoint

Fig. 13.  (Color online) (a) Double pulse test circuit. (b) Switching energy loss diagrams of the four devices.

DownLoad: Full-Size Img PowerPoint

Fig. 14.  (Color online) Proposed fabrication procedure of SG-CIMSOFET. (a) N-type epitaxial growth. (b) Form the base and N⁺ source region. (c) Form the P⁺ base and central implant region by tilt ion implantation. (d) Thermal oxidation. (e) Polysilicon deposition. (f) Polysilicon etching. (g) ILD oxide deposition and contact hole etching. (h) Metallization to form the source and drain.

DownLoad: Full-Size Img PowerPoint

Table 1.   Device characteristics comparison.

Parameter	Planar MOSFET	SG-MOSFET	CI-MOSFET	SG-CIMOSFET	Unit
N-drift doping concentration	2.2 × 1015	2.2 × 1015	3 × 1015	3 × 1015	cm–3
RON a	10.39	10.49	8.59	8.67	mΩ?cm2
EOX b	2.78	4.56	0.97	1.06	MV/cm
QG c	754.06	503.62	651.56	424.85	nC/cm2
QGD	216.92	126.98	77.21	42.49	nC/cm2
QTH	72.32	60.95	112.48	80.12	nC/cm2
QGD/QTH	2.99	2.08	0.69	0.53
CRSS d	42.27	32.19	11.16	7.72	pF/cm2
CISS d	14.99	13.93	22.31	15.21	nF/cm2
COSS d	316.21	315.78	365.96	365.96	nF/cm2
RON×QGD	2254	1332	663	368	mΩ?nC
RON×QG	7834	5282	5597	3683	mΩ?nC
RON×CRSS	439	338	96	67	mΩ?pF
a RON at VGS = 20 V, b EOX at VDS = 3000 V, c QG is the total gate charge, which is the gate charge from VGS = 0 to 20 V. d CISS, COSS, and CRSS are measured at VDS = 1500 V.

DownLoad: CSV

Table 2.   Switching characteristics comparison.

Parameter	Planar	SG-	CI-	SG-CI	Unit
TD-OFF	795.4	540.6	603.6	363.1	ns
TF	171.3	151.1	61.5	46.1	ns
TOFF	966.7	691.7	665.1	409.2	ns
TD-ON	159.2	146.1	227.5	154.1	ns
TR	134.2	115.6	48.2	36.4	ns
TON	293.4	261.7	275.7	190.5	ns
EOFF	15.1	13.4	4.4	3.1	mJ/cm2
EON	15.3	13.4	6.9	5.7	mJ/cm2
ETOTAL a	30.4	26.8	11.3	8.8	mJ/cm2
a ETOTAL is the sum of EON and EOFF.

DownLoad: CSV

[1]	Baliga B J. Power MOSFETs Fundamentals of power semiconductor devices. Boston, MA: Springer US, 2008, 276
[2]	Ji S Q, Zhang Z Y, Wang F. Overview of high voltage sic power semiconductor devices: Development and application. CES Trans Electr Mach Syst, 2017, 1, 254 doi: 10.23919/TEMS.2017.8086104
[3]	Cooper J A, Agarwal A. SiC power-switching devices-the second electronics revolution. Proc IEEE, 2002, 90, 956 doi: 10.1109/JPROC.2002.1021561
[4]	Wang G Y, Wang F, Magai G R, et al. Performance comparison of 1200V 100A SiC MOSFET and 1200V 100A silicon IGBT. 2013 IEEE Energy Convers Congr Expo, 2013, 3230
[5]	Nakamura T, Nakano Y, Aketa M, et al. High performance SiC trench devices with ultra-low Ron. 2011 International Electron Devices Meeting, 2011, 26.5.1
[6]	Sampath M, Morisette D T, Cooper J A. Comparison of single- and double-trench UMOSFETs in 4H-SiC. Mater Sci Forum, 2018, 924, 752 doi: 10.4028/www.scientific.net/MSF.924.752
[7]	Krishnaswami S, Das M, Hull B, et al. Gate oxide reliability of 4H-SiC MOS devices. 2005 IEEE International Reliability Physics Symposium, 2005, 592
[8]	Xu S M, Ren C H, Liang Y C, et al. Theoretical analysis and experimental characterization of the dummy-gated VDMOSFET. IEEE Trans Electron Devices, 2001, 48, 2168 doi: 10.1109/16.944212
[9]	Agarwal A, Han K, Baliga B J. 2.3 kV 4H-SiC accumulation-channel split-gate planar power MOSFETs with reduced gate charge. IEEE J Electron Devices Soc, 2020, 8, 499 doi: 10.1109/JEDS.2020.2991355
[10]	Han K, Baliga B J, Sung W. A novel 1.2 kV 4H-SiC buffered-gate (BG) MOSFET: Analysis and experimental results. IEEE Electron Device Lett, 2018, 39, 248 doi: 10.1109/LED.2017.2785771
[11]	Vudumula P, Kotamraju S. Design and optimization of 1.2-kV SiC planar inversion MOSFET using split dummy gate concept for high-frequency applications. IEEE Trans Electron Devices, 2019, 66, 5266 doi: 10.1109/TED.2019.2949459
[12]	Zhang Q C J, Duc J, Hull B, et al. CIMOSFET: A new MOSFET on SiC with a superior Ron·Qgd figure of merit. Mater Sci Forum, 2015, 821–823, 765
[13]	Zhang Q J, Wang G Y, Doan H, et al. Latest results on 1200 V 4H-SiC CIMOSFETs with Rsp, on of 3.9 mΩ·cm2 at 150 °C. 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2015, 89
[14]	TCAD Sentaurus Device Manual, Synopsys. 2016, Inc., Mountain View, CA, USA
[15]	Darwish M N, Lentz J L, Pinto M R, et al. An improved electron and hole mobility model for general purpose device simulation. IEEE Trans Electron Devices, 1997, 44, 1529 doi: 10.1109/16.622611
[16]	Mujtaba S A. Advanced mobility models for design and simulation of deep submicrometer MOSFETs. PhD Dissertation, Stanford University, 1995
[17]	Han K, Baliga B J, Sung W. Split-gate 1.2-kV 4H-SiC MOSFET: Analysis and experimental validation. IEEE Electron Device Lett, 2017, 38, 1437 doi: 10.1109/LED.2017.2738616
[18]	Wei J, Zhang M, Jiang H P, et al. Low ON-resistance SiC trench/planar MOSFET with reduced OFF-state oxide field and low gate charges. IEEE Electron Device Lett, 2016, 37, 1458 doi: 10.1109/LED.2016.2609599
[19]	Wei J, Zhang M, Jiang H P, et al. Dynamic degradation in SiC trench MOSFET with a floating p-shield revealed with numerical simulations. IEEE Trans Electron Devices, 2017, 64, 2592 doi: 10.1109/TED.2017.2697763
[20]	Ren M, Chen Z, Niu B, et al. A low miller capacitance VDMOS with shield gate and oxide trench. 2016 IEEE International Nanoelectronics Conference (INEC), 2016, 1
[21]	Basler T, Heer D, Peters D, et al. Practical aspects and body diode robustness of a 1200 V SiC trench MOSFET. International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2018, 1
[22]	Maerz A, Bertelshofer T, Bakran M, et al. A novel gate drive concept to eliminate parasitic turn-on of SiC MOSFET in low inductance power modules. International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2017, 1
[23]	Tian K, Hallén A, Qi J W, et al. An improved 4H-SiC trench-gate MOSFET with low ON-resistance and switching loss. IEEE Trans Electron Devices, 2019, 66, 2307 doi: 10.1109/TED.2019.2905636
[24]	Morikawa T, Ishigaki T, Shima A. Device design consideration for robust SiC VDMOSFET with self-aligned channels formed by tilted implantation. IEEE Trans Electron Devices, 2019, 66, 3447 doi: 10.1109/TED.2019.2924969
[25]	Zhou X T, Yue R F, Zhang J, et al. 4H-SiC trench MOSFET with floating/grounded junction barrier-controlled gate structure. IEEE Trans Electron Devices, 2017, 64, 4568 doi: 10.1109/TED.2017.2755721

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Received: 04 November 2020 Revised: 12 January 2021 Online: Accepted Manuscript: 18 March 2021Uncorrected proof: 12 April 2021Published: 01 June 2021

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Article Navigation >  Journal of Semiconductors  > 2021  >  42(6): 062803

Jongwoon Yoon, Kwangsoo Kim. A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. Journal of Semiconductors, 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803 ****J Yoon, K Kim, A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. J. Semicond., 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803.

Citation:

Jongwoon Yoon, Kwangsoo Kim. A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. Journal of Semiconductors, 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803 **** J Yoon, K Kim, A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. J. Semicond., 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803.

Jongwoon Yoon, Kwangsoo Kim. A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. Journal of Semiconductors, 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803 ****J Yoon, K Kim, A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. J. Semicond., 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803.

Citation:

Jongwoon Yoon, Kwangsoo Kim. A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. Journal of Semiconductors, 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803 **** J Yoon, K Kim, A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. J. Semicond., 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803.

PDF( 4084 KB)

A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

DOI: 10.1088/1674-4926/42/6/062803

• Jongwoon Yoon, 
• Kwangsoo Kim

• Department of Electronic Engineering, Sogang University, Seoul 04107, Korea

More Information

• Jongwoon Yoon：got his BS degree from Sogang University in 2020. Now he is in Master's course at Sogang University under the supervision of Prof. Kim. His research focuses on 4H-SiC MOSFET
• Kwangsoo Kim：received his BS degree in 1981, MS degree in 1983, and PhD at Sogang University in 1992. Since then, he joined Electronics and Telecommunications Research Institute (ETRI), Institute for Information Technology Advancement (IITA) and Daegu Gyeongbuk Institute of Science and Technology (DGIST). In 2008, he joined Sogang University as a full professor. His research focuses on 4H-SiC semiconductor devices and process
• Corresponding author: kimks@sogang.ac.kr
• Received Date: 2020-11-04
  
• Revised Date: 2021-01-12
• Published Date: 2021-06-10

Abstract

• Abstract

  A split gate MOSFET (SG-MOSFET) is widely known for reducing the reverse transfer capacitance (C_RSS). In a 3.3 kV class, the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field. In addition to the poor static performance, the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering (DIBL) caused by the high gate oxide electric field. As such, a 3.3 kV 4H-SiC split gate MOSFET with a grounded central implant region (SG-CIMOSFET) is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance. The SG-CIMOSFET has a significantly low on-resistance (R_ON) and maximum gate oxide field (E_OX) due to the central implant region. A grounded central implant region significantly reduces the C_RSS and gate drain charge (Q_GD) by partially screening the gate-to-drain capacitive coupling. Compared to a planar MOSFET, the SG MOSFET, central implant MOSFET (CIMOSFET), the SG-CIMOSFET improve the R_ON×Q_GD by 83.7%, 72.4% and 44.5%, respectively. The results show that the device features not only the smallest switching energy loss but also the fastest switching time.

   

  Keywords:
  • 4H-SiC, 
  • split gate, 
  • on-resistance, 
  • reverse transfer capacitance, 
  • switching energy loss, 
  • switching time
FullText(HTML)
References(25)

• References

  [1]	Baliga B J. Power MOSFETs Fundamentals of power semiconductor devices. Boston, MA: Springer US, 2008, 276
  [2]	Ji S Q, Zhang Z Y, Wang F. Overview of high voltage sic power semiconductor devices: Development and application. CES Trans Electr Mach Syst, 2017, 1, 254 doi: 10.23919/TEMS.2017.8086104
  [3]	Cooper J A, Agarwal A. SiC power-switching devices-the second electronics revolution. Proc IEEE, 2002, 90, 956 doi: 10.1109/JPROC.2002.1021561
  [4]	Wang G Y, Wang F, Magai G R, et al. Performance comparison of 1200V 100A SiC MOSFET and 1200V 100A silicon IGBT. 2013 IEEE Energy Convers Congr Expo, 2013, 3230
  [5]	Nakamura T, Nakano Y, Aketa M, et al. High performance SiC trench devices with ultra-low Ron. 2011 International Electron Devices Meeting, 2011, 26.5.1
  [6]	Sampath M, Morisette D T, Cooper J A. Comparison of single- and double-trench UMOSFETs in 4H-SiC. Mater Sci Forum, 2018, 924, 752 doi: 10.4028/www.scientific.net/MSF.924.752
  [7]	Krishnaswami S, Das M, Hull B, et al. Gate oxide reliability of 4H-SiC MOS devices. 2005 IEEE International Reliability Physics Symposium, 2005, 592
  [8]	Xu S M, Ren C H, Liang Y C, et al. Theoretical analysis and experimental characterization of the dummy-gated VDMOSFET. IEEE Trans Electron Devices, 2001, 48, 2168 doi: 10.1109/16.944212
  [9]	Agarwal A, Han K, Baliga B J. 2.3 kV 4H-SiC accumulation-channel split-gate planar power MOSFETs with reduced gate charge. IEEE J Electron Devices Soc, 2020, 8, 499 doi: 10.1109/JEDS.2020.2991355
  [10]	Han K, Baliga B J, Sung W. A novel 1.2 kV 4H-SiC buffered-gate (BG) MOSFET: Analysis and experimental results. IEEE Electron Device Lett, 2018, 39, 248 doi: 10.1109/LED.2017.2785771
  [11]	Vudumula P, Kotamraju S. Design and optimization of 1.2-kV SiC planar inversion MOSFET using split dummy gate concept for high-frequency applications. IEEE Trans Electron Devices, 2019, 66, 5266 doi: 10.1109/TED.2019.2949459
  [12]	Zhang Q C J, Duc J, Hull B, et al. CIMOSFET: A new MOSFET on SiC with a superior Ron·Qgd figure of merit. Mater Sci Forum, 2015, 821–823, 765
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• Fig. 1. (Color online) Schematic cross-sectional views of the MOSFETs. (a) Planar MOSFET. (b) SG-MOSFET. (c) CIMOSFET. (d) SG-CIMOSFET.
• Fig. 2. (Color online) (a) E_OX and R_ON changes of the planar MOSFET according to the W_JFET, and (b) influence of the L_split on BV, R_ON, Q_GD and E_OX in SG-MOSFET. BV is extracted at V_GS = 0 V and I_DS = 1 μA/cm².
• Fig. 3. (Color online) Electron current density distribution when breakdown occurs in the SG-MOSFET (a) when L_split = 0.5 μm, and (b) when L_split = 0.6 μm.
• Fig. 4. (Color online) (a) R_ON and BV relation in the SG-CIMOSFET according to change in W_P and H_P. (b)–(d) Impact ionization position when breakdown occurs in the SG-CIMOSFET according to change in W_P and H_P (the arrow indicates the breakdown point).
• Fig. 5. (a) E_OX changes and (b) Q_GD changes in the SG-CIMOSFET according to change in W_P and H_P. E_OX is obtained at V_DS = 3000 V and V_GS = 0 V.
• Fig. 6. The I–V characteristics of the four devices. R_ON and saturation current is obtained for V_GS = 20 V. BV is extracted at V_GS = 0 V and I_DS = 1 μA/cm².
• Fig. 7. (Color online) Off-state electric field distributions of the four devices when V_GS = 0 V and V_DS = 3000 V.
• Fig. 8. (Color online) The band diagram in the channel of the four devices at V_DS = 0 V, V_DS = 3000 V in off-state.
• Fig. 9. (Color online) (a) Reverse transfer capacitance characteristics (C_RSS) of the five devices. (b) Input capacitance (C_ISS) and drain source capacitance (C_DS) characteristics of the five devices (when V_GS = 0 V, AC signal of 1 MHz).
• Fig. 10. (Color online) (a) Depletion lines and reverse transfer capacitance models of the five devices when V_DS = 0 V, V_GS = 0 V. (b) Depletion lines of the five devices when V_DS = 800 V, V_GS = 0 V. The solid black line represents the depletion layer.
• Fig. 11. Gate charge characteristics and test circuit of the four devices.
• Fig. 12. Switching waveforms of the four devices. The active areas of all DUT are set to 1 cm².
• Fig. 13. (Color online) (a) Double pulse test circuit. (b) Switching energy loss diagrams of the four devices.
• Fig. 14. (Color online) Proposed fabrication procedure of SG-CIMSOFET. (a) N-type epitaxial growth. (b) Form the base and N⁺ source region. (c) Form the P⁺ base and central implant region by tilt ion implantation. (d) Thermal oxidation. (e) Polysilicon deposition. (f) Polysilicon etching. (g) ILD oxide deposition and contact hole etching. (h) Metallization to form the source and drain.