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J. Semicond. > 2017, Volume 38?>?Issue 11?> 115001

SEMICONDUCTOR INTEGRATED CIRCUITS

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

Lintao Liu, Yuhan Gao and Jun Deng

+ Author Affiliations

 Corresponding author: Lintao Liu, hitllt@163.com

DOI: 10.1088/1674-4926/38/11/115001

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Abstract: This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.

Key words: reconfigurable, mixed-signal, SoC, FPAA



[1]
George S, Kim S, Shah S, et al. A programmable and configurable mixed-mode FPAA SoC. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24: 2253 doi: 10.1109/TVLSI.2015.2504119
[2]
Schlottmann C, Nease S, Shapero S, et al. A mixed-mode FPAA SoC for analog-enhanced signal processing. Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
[3]
Hasler J, Kim S, Sahil S, et al. Transforming mixed-signal circuits class through SoC FPAA IC, PCB, and toolset. 2016 11th European Workshop on Microelectronics Education (EWME), 2016
[4]
Koneru S, Lee E K F, Chu C. A Flexible 2-D Switched-Capacitor FPAA Architecture and Its Mapping Algorithm. Proc CS, 1999, 1: 296 doi: 10.1109/MWSCAS.1999.867265
[5]
It’utuk H, Kang S M. A field-programmable analog array (FPAA) using switched-capacitor techniques. 1996 IEEE International Symposium on Circuits and Systems: Circuits and Systems Connecting the World, 1996 doi: 10.1109/ISCAS.1996.541896
[6]
Anderson D, Marcjan C, Bersch D, et al. A field programmable analog array and its application. Proceedings of CICC 97 - Custom Integrated Circuits Conference, 1997 doi: 10.1109/CICC.1997.606688
[7]
Collins M, Hasler J, George S. Analog systems education: an integrated toolset and FPAA SoC boards. 2015 IEEE International Conference on Microelectronics Systems Education (MSE), 2015 doi: 10.1109/MSE.2015.7160011
[8]
Deng J, Tan H Y, Liu L T, et al. Research of a mixed-signal programmable SoC based on FPAA. Pro ICMIAC, 2014 doi: 10.4028/wwww.scientific.net/AMM
[9]
Deng J, Huang X, Liu L T, et al. Design and implementation of a mixed SoC for IF digital software radio receiver. Proc ICACI, 2013 doi: 10.1109/ICACI.2013.6748513
[10]
Lee E, Gulak G. A CMOS field programmable analog array. IEEE J Solid-State Circuits, 1991, 26: 1860 doi: 10.1109/4.104162
[11]
Lee E, Gulak G. A Transconductor Based Field Programmable Analog Array. ISSCC Digest of Technical Papers, 1995: 198 doi: 10.1109/ISSCC.1995.535521
[12]
Pierzchala E, Perkowski M, Van Halen P, et al. Current-mode arnplifier/integrator for a field programmable analog array. ISSCC Digest of Technical Papers, 1995: 196 doi: 10.1109/ISSCC.1995.535520
[13]
Premont C, Grisel R, Abouchi N, et al. A current conveyor based field-programmable analog array. Analog Integrated Circuits and Signal Processing, 1998, 17: 105 doi: 10.1023/A:1008202016480
[14]
Embabi S, Quan X, Oki N, et al. A current-mode rased field-programmable analog array for signal processing applications. Analog Integrated Circuits and Signal Processing, 1998, 17: 125 doi: 10.1023/A:1008254100550
[15]
Li L, Xu M Y, Huang X F, et al. A 12 bit 500 MS/S SHA-less ADC in 0.18 μm CMOS. 2016 IEEE International Nanoelectronics Conference (INEC), 2016: 1 doi: 10.1109/INEC.2016.7589282
[16]
Murmann B, Boser B. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J Solid-State Circuits, 2003, 38(2): 2004 doi: 10.1109/JSSC.2003.819167
[17]
Brandolini M, Shin Y J, Raviprakash K, et al. A 5 GS/s 150 mW 10 b SHA-less pipelined/SAR hybrid ADC for direct-sampling systems in 28 nm CMOS. IEEE J Solid-State Circuits, 2015, 50: 2922 doi: 10.1109/JSSC.2015.2464684
[18]
Mercer D A. Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18-m CMOS. IEEE J Solid-State Circuits, 2007, 42(8): 1688 doi: 10.1109/JSSC.2007.900279
[19]
Chen T, Gielen G G E. The analysis and improvement of a current-steering DACs dynamic SFDR—The cell-dependent delay differences. IEEE Trans Circuits Syst, 2006, 53(1): 3 doi: 10.1109/TCSI.2005.854409
[20]
Müller S, Hanay O, Negra R. Current-steering DAC linearisation by impedance transformation. 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016,: 1 doi: 10.1109/NORCHIP.2016.7792900
[21]
Liu M L, Zhu Z M Yang Y T. A high-SFDR 14-bit 500 MS/s current-steering D/A converter in 0.18 m CMOS. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2015, 23: 3148 doi: 10.1109/TVLSI.2014.2386332
[22]
Chou F T, Hung C C. Glitch energy reduction and sfdr enhancement techniques for low-power binary-weighted current-steering DAC. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24: 2407 doi: 10.1109/TVLSI.2015.2503727
Fig. 1.  (Color online) Architecture of proposed SoC.

Fig. 2.  Architecture of FPAA IP.

Fig. 3.  Structure of CAB.

Fig. 4.  Structure of dynamic reconfigurable circuit.

Fig. 5.  Structure of ADC IP.

Fig. 6.  Architecture of DAC IP.

Fig. 7.  Photomicrograph of proposed SoC.

Fig. 8.  (Color online) The measurement system.

Fig. 9.  (Color online) Partial configuration results of FPAA-based SoC.

Fig. 10.  (Color online) Measurement results of ADC IP. (a) Static measurement results. (b) Dynamic measurement results.

Fig. 11.  (Color online) Measurement results of DAC IP. (a) Static measurement results. (b) SFDR @fCLK = 200 MHz/fout = 20 MHz.

Fig. 12.  Typical signal processing flow of FPAA-based SoC.

Fig. 13.  (Color online) The demonstration processing system of FPAA-based SoC. (a) The debugging user interface. (b) The output waveform of DAC. (c) The FFT analysis of the output waveform.

Table 1.   Configuration codes of a gain amplifier with 3 times.

Register bank Register address Configuration code
1 0x0e, 0x0f, 0x11, 0x13, 0x14, 0x15, 0x17, 0x1c, 0x1e 0x01, 0x48, 0x48, 0x01, 0x20, 0x10, 0x20, 0x48, 0x48
2 0x00, 0x02, 0x03, 0x05, 0x06, 0x07, 0x08, 0x11, 0x1f 0xa9, 0x10, 0x06, 0x10, 0xff, 0x01, 0x18, 0x07, 0x04
3 0x01, 0x02, 0x03, 0x04, 0x0b, 0x1f 0xc1, 0xad, 0xc1, 0xac, 0x98, 0x10
DownLoad: CSV

Table 2.   Specifications of FPAA as a programmable of gain amplifier.

Parameter Condition (TA = 25 °C) Typ Unit
Gain Configuration codes of register bank2: 0xfa, 0x10, 0x19, 0x10, 0xff, 0x01, 0x18, 0x07, 0x04 1.0 Times
Configuration codes of register bank2: 0xc8, 0x10, 0x02, 0x10, 0xff, 0x01, 0x18, 0x07, 0x04 2.0
Configuration codes of register bank2: 0xa9, 0x10, 0x06, 0x10, 0xff, 0x01, 0x18, 0x07, 0x04 3.0
Configuration codes of register bank2: 0xb0, 0x10, 0x04, 0x10, 0xff, 0x01, 0x18, 0x07, 0x04 5.0
Configuration codes of register bank2: 0xaf, 0x10, 0x02, 0x10, 0xff, 0x01, 0x18, 0x07, 0x04 8.0
Gain resolution 3 Bits
Gain bandwidth products CL = 10 nF 15 MHz
Nonlinearity For all gain ±0.005 %
Noise referred to the input @ 1 kHz 18 nV/ $\sqrt {{\rm Hz}} $
DownLoad: CSV

Table 3.   The output sine-wave of FPAA based SoC.

Parameter Condition Typ Unit
Frequency TA = 25 °C; ADC input frequency: fin = 200 kHz; ADC input amplitude: 500 mV; ADC clock frequency: fCLK_ADC = 200 MHz;CPU working frequency: fCLK_CPU = 200 MHz;DAC clock frequency: fCLK_DAC = 200 MHz; 196.9 kHz
Amplitude 720 mV
Resolution 14 Bit
DNL ±2.5 LSB
INL ±5.5 LSB
Noise floor 105 dB
SFRD 82 dB
SNR 76 dB
DownLoad: CSV
[1]
George S, Kim S, Shah S, et al. A programmable and configurable mixed-mode FPAA SoC. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24: 2253 doi: 10.1109/TVLSI.2015.2504119
[2]
Schlottmann C, Nease S, Shapero S, et al. A mixed-mode FPAA SoC for analog-enhanced signal processing. Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
[3]
Hasler J, Kim S, Sahil S, et al. Transforming mixed-signal circuits class through SoC FPAA IC, PCB, and toolset. 2016 11th European Workshop on Microelectronics Education (EWME), 2016
[4]
Koneru S, Lee E K F, Chu C. A Flexible 2-D Switched-Capacitor FPAA Architecture and Its Mapping Algorithm. Proc CS, 1999, 1: 296 doi: 10.1109/MWSCAS.1999.867265
[5]
It’utuk H, Kang S M. A field-programmable analog array (FPAA) using switched-capacitor techniques. 1996 IEEE International Symposium on Circuits and Systems: Circuits and Systems Connecting the World, 1996 doi: 10.1109/ISCAS.1996.541896
[6]
Anderson D, Marcjan C, Bersch D, et al. A field programmable analog array and its application. Proceedings of CICC 97 - Custom Integrated Circuits Conference, 1997 doi: 10.1109/CICC.1997.606688
[7]
Collins M, Hasler J, George S. Analog systems education: an integrated toolset and FPAA SoC boards. 2015 IEEE International Conference on Microelectronics Systems Education (MSE), 2015 doi: 10.1109/MSE.2015.7160011
[8]
Deng J, Tan H Y, Liu L T, et al. Research of a mixed-signal programmable SoC based on FPAA. Pro ICMIAC, 2014 doi: 10.4028/wwww.scientific.net/AMM
[9]
Deng J, Huang X, Liu L T, et al. Design and implementation of a mixed SoC for IF digital software radio receiver. Proc ICACI, 2013 doi: 10.1109/ICACI.2013.6748513
[10]
Lee E, Gulak G. A CMOS field programmable analog array. IEEE J Solid-State Circuits, 1991, 26: 1860 doi: 10.1109/4.104162
[11]
Lee E, Gulak G. A Transconductor Based Field Programmable Analog Array. ISSCC Digest of Technical Papers, 1995: 198 doi: 10.1109/ISSCC.1995.535521
[12]
Pierzchala E, Perkowski M, Van Halen P, et al. Current-mode arnplifier/integrator for a field programmable analog array. ISSCC Digest of Technical Papers, 1995: 196 doi: 10.1109/ISSCC.1995.535520
[13]
Premont C, Grisel R, Abouchi N, et al. A current conveyor based field-programmable analog array. Analog Integrated Circuits and Signal Processing, 1998, 17: 105 doi: 10.1023/A:1008202016480
[14]
Embabi S, Quan X, Oki N, et al. A current-mode rased field-programmable analog array for signal processing applications. Analog Integrated Circuits and Signal Processing, 1998, 17: 125 doi: 10.1023/A:1008254100550
[15]
Li L, Xu M Y, Huang X F, et al. A 12 bit 500 MS/S SHA-less ADC in 0.18 μm CMOS. 2016 IEEE International Nanoelectronics Conference (INEC), 2016: 1 doi: 10.1109/INEC.2016.7589282
[16]
Murmann B, Boser B. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J Solid-State Circuits, 2003, 38(2): 2004 doi: 10.1109/JSSC.2003.819167
[17]
Brandolini M, Shin Y J, Raviprakash K, et al. A 5 GS/s 150 mW 10 b SHA-less pipelined/SAR hybrid ADC for direct-sampling systems in 28 nm CMOS. IEEE J Solid-State Circuits, 2015, 50: 2922 doi: 10.1109/JSSC.2015.2464684
[18]
Mercer D A. Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18-m CMOS. IEEE J Solid-State Circuits, 2007, 42(8): 1688 doi: 10.1109/JSSC.2007.900279
[19]
Chen T, Gielen G G E. The analysis and improvement of a current-steering DACs dynamic SFDR—The cell-dependent delay differences. IEEE Trans Circuits Syst, 2006, 53(1): 3 doi: 10.1109/TCSI.2005.854409
[20]
Müller S, Hanay O, Negra R. Current-steering DAC linearisation by impedance transformation. 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016,: 1 doi: 10.1109/NORCHIP.2016.7792900
[21]
Liu M L, Zhu Z M Yang Y T. A high-SFDR 14-bit 500 MS/s current-steering D/A converter in 0.18 m CMOS. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2015, 23: 3148 doi: 10.1109/TVLSI.2014.2386332
[22]
Chou F T, Hung C C. Glitch energy reduction and sfdr enhancement techniques for low-power binary-weighted current-steering DAC. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24: 2407 doi: 10.1109/TVLSI.2015.2503727

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    Received: 08 May 2017 Revised: 06 June 2017 Online: Uncorrected proof: 30 October 2017Accepted Manuscript: 13 November 2017Published: 01 November 2017

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      Lintao Liu, Yuhan Gao, Jun Deng. Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays[J]. Journal of Semiconductors, 2017, 38(11): 115001. doi: 10.1088/1674-4926/38/11/115001 ****L T Liu, Y H Gao, J Deng. Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays[J]. J. Semicond., 2017, 38(11): 115001. doi: 10.1088/1674-4926/38/11/115001.
      Citation:
      Lintao Liu, Yuhan Gao, Jun Deng. Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays[J]. Journal of Semiconductors, 2017, 38(11): 115001. doi: 10.1088/1674-4926/38/11/115001 ****
      L T Liu, Y H Gao, J Deng. Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays[J]. J. Semicond., 2017, 38(11): 115001. doi: 10.1088/1674-4926/38/11/115001.

      Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

      DOI: 10.1088/1674-4926/38/11/115001

      • Chongqing Acoustic-Optic-Electic Co., Ltd., China Electronics Technology Group CORP., Chongqing 400060, China

      Funds:

      Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

      More Information
      • Corresponding author: hitllt@163.com
      • Received Date: 2017-05-08
      • Revised Date: 2017-06-06
      • Published Date: 2017-11-01

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