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J. Semicond. > 2016, Volume 37?>?Issue 9?> 095001

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SEMICONDUCTOR INTEGRATED CIRCUITS

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

Yiqi Mao^{1, 2}, Tongqiang Gao^{1, 2}, Xiaodong Xu¹, Haigang Yang^{1, 2,} and Xinxia Cai^{1, 2}

+ Author Affiliations + Find other works by these authors

• 1. Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, ChinaInstitute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
• 2. University of Chinese Academy of Sciences, Beijing 100039, ChinaUniversity of Chinese Academy of Sciences, Beijing 100039, China

• Yiqi Mao
• Tongqiang Gao
• Xiaodong Xu
• Haigang Yang
• Xinxia Cai

 Corresponding author: Yang Haigang,yanghg@mail.ie.ac.cn

DOI: 10.1088/1674-4926/37/9/095001

• Abstract
• Full Text(HTML)
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• References(12)
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Abstract: A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm². It achieves a sensitivity of -80 dBm for 10^-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.

Key words: super-regenerative receiver, wake-up circuit, EEG, OOK, CMOS

References

[1]	Armstrong E H. Some recent developments of regenerative circuits. Proceedings of the Institute of Radio Engineers, 1922, 10(4): 244 http://cn.bing.com/academic/profile?id=2150943617&encoded=0&v=paper_preview&mkt=zh-cn
[2]	Favre P, Joehl N, Vouilloz A, et al. A 2-V 600-μ A 1-GHz BiCMOS super-regenerative receiver for ISM application. IEEE J Solid-State Circuit, 1998, 33(12): 2186 doi: 10.1109/4.735703
[3]	Zahabi A, Anis M, Ortmanns M. 2.4 GHz super-regeneration amplifier with degenerative quenching technique for RF-pulse width transceiver. IEEE International Symposium on Circuits and System (ISCAS), 2012: 2147 http://cn.bing.com/academic/profile?id=1967046438&encoded=0&v=paper_preview&mkt=zh-cn
[4]	Otis B, Chee Y H, Rabaey J. A 400μ W-RX, 1.6 mW-TX super-regenerative transceiver for wireless sensor networks. Solid-State Circuits Conference (ISSCC), 2005, 1: 396
[5]	Chen J Y, Flynn M P, Hayes J P. A fully integrated auto-calibrated super-regenerative receiver in 0.13-μm CMOS. IEEE J Solid-State Circuits, 2007, 42(9): 1976 doi: 10.1109/JSSC.2007.903092
[6]	Meyer R. Low-power monolithic RF peak detector analysis. IEEE J Solid State Circuits, 1995, 30(1): 65 doi: 10.1109/4.350192
[7]	Rabaey J M, Chandrakasam A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. Electronics & VLSI, 2002 http://cn.bing.com/academic/profile?id=2157024459&encoded=0&v=paper_preview&mkt=zh-cn
[8]	Chen J Y. Design of low-power super-regenerative receivers. The University of Michigan, 2006
[9]	Barner R, Liu J. A 0.8 V 1.52 MHz MSVC relaxation oscillator with inverted mirror feedback reference for UHF RFID. IEEE Custom Integrated Circuits Conference (CICC), 2006: 769
[10]	Harrison R R, Charles C. A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid-State Circuits, 2003, 38(6): 958 doi: 10.1109/JSSC.2003.811979
[11]	Zhu Wenrui, Yang Haigang, Gao Tongqiang, et al. A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness. Journal of Semiconductors, 2013, 34(8): 085011 doi: 10.1088/1674-4926/34/8/085011
[12]	Liu Y H, Lin T H. A delta-sigma pulse-width digitization technique for super-regenerative receivers. IEEE J Solid State-Circuits, 2010, 45(10): 2066 doi: 10.1109/JSSC.2010.2061614

Fig. 1.  The topology of EEG chip

DownLoad: Full-Size Img PowerPoint

Fig. 2.  (a) The Architecture of the proposed receiver. (b) The waveforms of the proposed receive

DownLoad: Full-Size Img PowerPoint

Fig. 3.  The schematic of proposed IA and VCO circuits

DownLoad: Full-Size Img PowerPoint

Fig. 4.  The schematic of envelope detector

DownLoad: Full-Size Img PowerPoint

Fig. 5.  (a) Relaxed oscillator and Vgs–R reference. (b) Quench signal generator.

DownLoad: Full-Size Img PowerPoint

Fig. 6.  Output waveform of relaxed oscillator and quench signal generator.

DownLoad: Full-Size Img PowerPoint

Fig. 7.  Schematic of proposed PWD

DownLoad: Full-Size Img PowerPoint

Fig. 8.  The amplitude–frequency response of the cascaded filter at different processed corners.

DownLoad: Full-Size Img PowerPoint

Fig. 9.  Microphotograph of the SRR receiver

DownLoad: Full-Size Img PowerPoint

Fig. 10.  The measured S11 of IA

DownLoad: Full-Size Img PowerPoint

Fig. 11.  Measured waveforms of SRR

DownLoad: Full-Size Img PowerPoint

Table 1.   Performance comparison between simulation and measured results

Table 2.   Performance comparison with other works

[1]	Armstrong E H. Some recent developments of regenerative circuits. Proceedings of the Institute of Radio Engineers, 1922, 10(4): 244 http://cn.bing.com/academic/profile?id=2150943617&encoded=0&v=paper_preview&mkt=zh-cn
[2]	Favre P, Joehl N, Vouilloz A, et al. A 2-V 600-μ A 1-GHz BiCMOS super-regenerative receiver for ISM application. IEEE J Solid-State Circuit, 1998, 33(12): 2186 doi: 10.1109/4.735703
[3]	Zahabi A, Anis M, Ortmanns M. 2.4 GHz super-regeneration amplifier with degenerative quenching technique for RF-pulse width transceiver. IEEE International Symposium on Circuits and System (ISCAS), 2012: 2147 http://cn.bing.com/academic/profile?id=1967046438&encoded=0&v=paper_preview&mkt=zh-cn
[4]	Otis B, Chee Y H, Rabaey J. A 400μ W-RX, 1.6 mW-TX super-regenerative transceiver for wireless sensor networks. Solid-State Circuits Conference (ISSCC), 2005, 1: 396
[5]	Chen J Y, Flynn M P, Hayes J P. A fully integrated auto-calibrated super-regenerative receiver in 0.13-μm CMOS. IEEE J Solid-State Circuits, 2007, 42(9): 1976 doi: 10.1109/JSSC.2007.903092
[6]	Meyer R. Low-power monolithic RF peak detector analysis. IEEE J Solid State Circuits, 1995, 30(1): 65 doi: 10.1109/4.350192
[7]	Rabaey J M, Chandrakasam A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. Electronics & VLSI, 2002 http://cn.bing.com/academic/profile?id=2157024459&encoded=0&v=paper_preview&mkt=zh-cn
[8]	Chen J Y. Design of low-power super-regenerative receivers. The University of Michigan, 2006
[9]	Barner R, Liu J. A 0.8 V 1.52 MHz MSVC relaxation oscillator with inverted mirror feedback reference for UHF RFID. IEEE Custom Integrated Circuits Conference (CICC), 2006: 769
[10]	Harrison R R, Charles C. A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid-State Circuits, 2003, 38(6): 958 doi: 10.1109/JSSC.2003.811979
[11]	Zhu Wenrui, Yang Haigang, Gao Tongqiang, et al. A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness. Journal of Semiconductors, 2013, 34(8): 085011 doi: 10.1088/1674-4926/34/8/085011
[12]	Liu Y H, Lin T H. A delta-sigma pulse-width digitization technique for super-regenerative receivers. IEEE J Solid State-Circuits, 2010, 45(10): 2066 doi: 10.1109/JSSC.2010.2061614

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Received: 04 January 2016 Revised: 12 April 2016 Online: Published: 01 September 2016

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Article Navigation >  Journal of Semiconductors  > 2016  >  37(9): 095001

Yiqi Mao, Tongqiang Gao, Xiaodong Xu, Haigang Yang, Xinxia Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. Journal of Semiconductors, 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001 ****Y Q Mao, T Q Gao, X D Xu, H G Yang, X X Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. J. Semicond., 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001.

Citation:

Yiqi Mao, Tongqiang Gao, Xiaodong Xu, Haigang Yang, Xinxia Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. Journal of Semiconductors, 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001 **** Y Q Mao, T Q Gao, X D Xu, H G Yang, X X Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. J. Semicond., 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001.

Yiqi Mao, Tongqiang Gao, Xiaodong Xu, Haigang Yang, Xinxia Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. Journal of Semiconductors, 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001 ****Y Q Mao, T Q Gao, X D Xu, H G Yang, X X Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. J. Semicond., 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001.

Citation:

Yiqi Mao, Tongqiang Gao, Xiaodong Xu, Haigang Yang, Xinxia Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. Journal of Semiconductors, 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001 **** Y Q Mao, T Q Gao, X D Xu, H G Yang, X X Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. J. Semicond., 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001.

PDF( 326 KB)

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

DOI: 10.1088/1674-4926/37/9/095001

• Yiqi Mao^1,2, 
• Tongqiang Gao^1,2, 
• Xiaodong Xu¹, 
• Haigang Yang^1,2,  , 
• Xinxia Cai^1,2

• 1.

  Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China

• 2.

  University of Chinese Academy of Sciences, Beijing 100039, China

Funds:

National Natural Science Foundation of China 61474120

National Basic Research Program of China 2014CB744600

Project supported by the National Basic Research Program of China (No. 2014CB744600) and the National Natural Science Foundation of China (No. 61474120).

More Information

• Corresponding author: Yang Haigang,yanghg@mail.ie.ac.cn
• Received Date: 2016-01-04
  
• Revised Date: 2016-04-12
• Published Date: 2016-09-01

Abstract

• Abstract

  A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm². It achieves a sensitivity of -80 dBm for 10^-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.

   

  Keywords:
  • super-regenerative receiver, 
  • wake-up circuit, 
  • EEG, 
  • OOK, 
  • CMOS
FullText(HTML)
References(12)

• References

  [1]	Armstrong E H. Some recent developments of regenerative circuits. Proceedings of the Institute of Radio Engineers, 1922, 10(4): 244 http://cn.bing.com/academic/profile?id=2150943617&encoded=0&v=paper_preview&mkt=zh-cn
  [2]	Favre P, Joehl N, Vouilloz A, et al. A 2-V 600-μ A 1-GHz BiCMOS super-regenerative receiver for ISM application. IEEE J Solid-State Circuit, 1998, 33(12): 2186 doi: 10.1109/4.735703
  [3]	Zahabi A, Anis M, Ortmanns M. 2.4 GHz super-regeneration amplifier with degenerative quenching technique for RF-pulse width transceiver. IEEE International Symposium on Circuits and System (ISCAS), 2012: 2147 http://cn.bing.com/academic/profile?id=1967046438&encoded=0&v=paper_preview&mkt=zh-cn
  [4]	Otis B, Chee Y H, Rabaey J. A 400μ W-RX, 1.6 mW-TX super-regenerative transceiver for wireless sensor networks. Solid-State Circuits Conference (ISSCC), 2005, 1: 396
  [5]	Chen J Y, Flynn M P, Hayes J P. A fully integrated auto-calibrated super-regenerative receiver in 0.13-μm CMOS. IEEE J Solid-State Circuits, 2007, 42(9): 1976 doi: 10.1109/JSSC.2007.903092
  [6]	Meyer R. Low-power monolithic RF peak detector analysis. IEEE J Solid State Circuits, 1995, 30(1): 65 doi: 10.1109/4.350192
  [7]	Rabaey J M, Chandrakasam A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. Electronics & VLSI, 2002 http://cn.bing.com/academic/profile?id=2157024459&encoded=0&v=paper_preview&mkt=zh-cn
  [8]	Chen J Y. Design of low-power super-regenerative receivers. The University of Michigan, 2006
  [9]	Barner R, Liu J. A 0.8 V 1.52 MHz MSVC relaxation oscillator with inverted mirror feedback reference for UHF RFID. IEEE Custom Integrated Circuits Conference (CICC), 2006: 769
  [10]	Harrison R R, Charles C. A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid-State Circuits, 2003, 38(6): 958 doi: 10.1109/JSSC.2003.811979
  [11]	Zhu Wenrui, Yang Haigang, Gao Tongqiang, et al. A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness. Journal of Semiconductors, 2013, 34(8): 085011 doi: 10.1088/1674-4926/34/8/085011
  [12]	Liu Y H, Lin T H. A delta-sigma pulse-width digitization technique for super-regenerative receivers. IEEE J Solid State-Circuits, 2010, 45(10): 2066 doi: 10.1109/JSSC.2010.2061614

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• Fig. 1. The topology of EEG chip
• Fig. 2. (a) The Architecture of the proposed receiver. (b) The waveforms of the proposed receive
• Fig. 3. The schematic of proposed IA and VCO circuits
• Fig. 4. The schematic of envelope detector
• Fig. 5. (a) Relaxed oscillator and Vgs–R reference. (b) Quench signal generator.
• Fig. 6. Output waveform of relaxed oscillator and quench signal generator.
• Fig. 7. Schematic of proposed PWD
• Fig. 8. The amplitude–frequency response of the cascaded filter at different processed corners.
• Fig. 9. Microphotograph of the SRR receiver
• Fig. 10. The measured S11 of IA
• Fig. 11. Measured waveforms of SRR