J. Semicond. > 2016, Volume 37?>?Issue 7?> 075005

SEMICONDUCTOR INTEGRATED CIRCUITS

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

Mingyuan Yu1, Ting Li2, Jiaqi Yang1, Shuangshuang Zhang1, Fujiang Lin1 and Lin He1,

+ Author Affiliations

 Corresponding author: He Lin, Email: helin77@ustc.edu.cn

DOI: 10.1088/1674-4926/37/7/075005

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Abstract: This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μ W at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2.

Key words: SAR ADC, low power, high speed, subrange, modified SAR logic



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Pang W Y, Wang C S, Chang Y K, et al. A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications. IEEE A-SSCC, 2009:149
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.  Asynchronous SAR ADC with monotonic switching procedure.

.  Architecture of the proposed SAR ADC.

.  (Color online) Simulated waveforms of the CDAC (dashed curve) and the MDAC (dotted curve).

.  Schematic of the dynamic comparator.

.  Trigger signal generator for comparators in coarse ADC.

.  Diagram of (a) the conventional SAR logicand (b) the modified SAR logic.

.  (Color online) Simulated waveforms of modified (above) and conventional (below) SAR logics.

.  Schematic and timing diagram of the dynamic latch.

.  Schematic and timing diagram of the modified DFF.

.  Die photograph of the proposed SAR ADC.

.  Measured DNL and INL of the proposed SAR ADC.

.  16384 points FFT @ 50 MS/s with 23.125-MHz input.

.   Performance comparison with other published SAR ADCs.

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[1]
Pang W Y, Wang C S, Chang Y K, et al. A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications. IEEE A-SSCC, 2009:149
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    History

    Received: 23 November 2015 Revised: Online: Published: 01 July 2016

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      Mingyuan Yu, Ting Li, Jiaqi Yang, Shuangshuang Zhang, Fujiang Lin, Lin He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process[J]. Journal of Semiconductors, 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005 ****M Y Yu, T Li, J Q Yang, S S Zhang, F J Lin, L He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process[J]. J. Semicond., 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005.
      Citation:
      Mingyuan Yu, Ting Li, Jiaqi Yang, Shuangshuang Zhang, Fujiang Lin, Lin He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process[J]. Journal of Semiconductors, 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005 ****
      M Y Yu, T Li, J Q Yang, S S Zhang, F J Lin, L He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process[J]. J. Semicond., 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005.

      A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

      DOI: 10.1088/1674-4926/37/7/075005
      • 1.

        Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China

      • 2.

        Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China

      Funds:

      The authors would like to thank the lab center of information science in USTC for EDA tools support and Media tek Inc for the scholarship.

      More Information
      • Corresponding author: He Lin, Email: helin77@ustc.edu.cn
      • Received Date: 2015-11-23
      • Accepted Date: 2016-01-18
      • Published Date: 2016-07-25

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