Abstract: This paper presents an optimized SRAM that is repairable and dissipates less power.To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up.In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed.The optimized LPSR SRAM64K×32 is used in SoC and the testing method of the LPSR SRAM64K×32 is also discussed.The SoC design is successfully implemented in the Chartered 90nm CMOS process.The SoC chip occupies 56mm×56mm of die area and the power dissipation is 1997mW.The test results indicate that LPSR SRAM64K×32 obtains 17301% power savings and the yield of the LPSR SRAM64K×32s per wafer is improved by 13255%.

Key words: optimization, LPSR SRAM, redundancy logic, power on/off states