Abstract: Two parameters, one called the unified stacking factor (USF) and the other called the circuit virtual stacking factor (VSF), are defined based on the relationship between the transistor stacking effect and the leakage current of standard cells.A VSF-based leakage power evaluation model is then developed and used for evaluating and reducing the leakage power of CMOS combinational circuits.Experiments show that the VSF model is not needed for Hspice simulation when evaluating leakage power.For ISCAS85 benchmark circuits, satisfactory leakage power reduction can be achieved, and the optimization speed can be accelerated greatly.

Key words: unified stacking factor, virtual stacking factor, leakage power evaluation model, CMOS combinational circuit