Abstract: In this paper,a detailed analysis of a phase interpolator for clock recovery is presented.A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model.The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases.A new encoding pattern is given to solve this problem.Analysis in the circuit domain was also undertaken.The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator.To alleviate this undesired effect,two adjustable-RC buffers are added at the input of the PI.Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed.The power dissipation of the phase interpolator is 1mW with a 1.2V power supply.Experiment results show that the phase interpolator has a monotone output phase and good linearity.

Key words: phase interpolator, clock and data recovery, CMOS