Abstract: We discuss major factors that affect the performance of a CMOS analog sampling switch.We also propose a novel architecture that is aimed to compensate the effects of clock feedthrough in Bootstrapped switches.It breaks the tradeoff between speed and resolution in Bootstrapped switch design.The entire circuit is simulated by Hspice in SMIC’s 0.25μm standard CMOS AMS process.The proposed sampling switch achieves a spurious free dynamic range of 92dB and signal to noise and distortion ratio of 82dB for a 233MHz,2V Vp-p input signal,sampled at a rate of 50MS/s,clock rise/fall time 0.1ns.Also,the maximum hold step error is reduced from 5.5mV to 90μV.This method is especially useful for high speed high resolution ADCs.

Key words: bootstrapped switch, nonlinear, clock feedthrough compensated, hold error, ADC