Abstract: Repeater optimization is key for SOC interconnect delay design.This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines.A Lagrangian function is presented to find the number of repeaters and their sizes required for minimizing area and power overhead with a target delay constraint.Based on 65nm CMOS technology,the computed results of the intermediate and global lines show that the proposed model can significantly reduce the area and power of interconnect lines and is especially suitable for global lines.The best performance will be achieved with the longer line.The proposed model can be integrated into repeater design methodology and CAD tools for interconnect planning in nanometer SOCs.

Key words: distributed RLC, interconnect power dissipation and area, target delay, Lagrangian function, nanometer CMOS