Abstract: We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition,low jitter,and wide tuning range.A dual-edge-triggered phase frequency detector (PFD) and a self-regulated voltage controlled oscillator (VCO) are employed in this design to realize the aforementioned properties.Measured results show that the experimental chip,implemented in a standard 0.5μm 5V CMOS logic process,has an acquisition time of about 150ns at 37% frequency variation and an output RMS jitter of 39ps at 640MHz.

Key words: PLL, fast acquisition, low jitter, wide tuning range