Abstract: A fractional-Nfrequency synthesizer for 433/868MHz SRD applications is implemented in a 0.35μm CMOS process.A wide-band VCO and an AFC are used to cover the desired bands.A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise.The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency,and a fractional spur of less than -60dBc.The chip area is 1.5mm×1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.

Key words: short range device, phase locked loop, adaptive frequency calibration, frequency synthesizer, sigma-delta