A Low Jitter PLL in a 90nm CMOS Digital Process

Yin Haifeng; Wang Feng; Liu Jun; Mao Zhigang

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J. Semicond. > 2008, Volume 29?>?Issue 8?> 1511-1516

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A Low Jitter PLL in a 90nm CMOS Digital Process

Yin Haifeng, Wang Feng, Liu Jun and Mao Zhigang

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Abstract: A low jitter phase-locked loop (PLL) that does not need analog resistors and capacitors is designed and fabricated in a 90nm CMOS digital process.The metal parasitic capacitor is used in the PLL loop filter.Test results show that when the PLL is locked on 1.989GHz,the RMS jitter is 3.7977ps,the peak-to-peak jitter is 31.225ps,and the power consumption is about 9mW.The locked output frequency range is from 125MHz to 2.7GHz.

Key words: PLL, PFD, charge pump, VCO

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Received: 18 August 2015 Revised: 26 March 2008 Online: Published: 01 August 2008

Article Navigation > Journal of Semiconductors > 2008 > 29(8): 1511-1516

Yin Haifeng, Wang Feng, Liu Jun, Mao Zhigang. A Low Jitter PLL in a 90nm CMOS Digital Process[J]. Journal of Semiconductors, 2008, 29(8): 1511-1516. ****Yin H F, Wang F, Liu J, Mao Z G. A Low Jitter PLL in a 90nm CMOS Digital Process[J]. J. Semicond., 2008, 29(8): 1511.

Citation:

Yin Haifeng, Wang Feng, Liu Jun, Mao Zhigang. A Low Jitter PLL in a 90nm CMOS Digital Process[J]. Journal of Semiconductors, 2008, 29(8): 1511-1516. ****

Yin H F, Wang F, Liu J, Mao Z G. A Low Jitter PLL in a 90nm CMOS Digital Process[J]. J. Semicond., 2008, 29(8): 1511.

Citation:

Yin Haifeng, Wang Feng, Liu Jun, Mao Zhigang. A Low Jitter PLL in a 90nm CMOS Digital Process[J]. Journal of Semiconductors, 2008, 29(8): 1511-1516. ****

Yin H F, Wang F, Liu J, Mao Z G. A Low Jitter PLL in a 90nm CMOS Digital Process[J]. J. Semicond., 2008, 29(8): 1511.

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A Low Jitter PLL in a 90nm CMOS Digital Process

Microelectronic Center,Harbin Institute of Technology,Harbin 150001,China
Haokai Microeletronics (Shanghai) Corporation,Shanghai 200127,China
Haokai Microeletronics (Shanghai) Corporation,Shanghai 200127,China
Microelectronic Center,Harbin Institute of Technology,Harbin 150001,China

Received Date: 2015-08-18
Accepted Date: 2008-01-07
Revised Date: 2008-03-26
Published Date: 2008-08-02

Abstract

Abstract

A low jitter phase-locked loop (PLL) that does not need analog resistors and capacitors is designed and fabricated in a 90nm CMOS digital process.The metal parasitic capacitor is used in the PLL loop filter.Test results show that when the PLL is locked on 1.989GHz,the RMS jitter is 3.7977ps,the peak-to-peak jitter is 31.225ps,and the power consumption is about 9mW.The locked output frequency range is from 125MHz to 2.7GHz.
- PLL,
- PFD,
- charge pump,
- VCO

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A Low Jitter PLL in a 90nm CMOS Digital Process

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