Abstract: Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips.The memory bit cell is designed with conventional single-poly pMOS transistors,based on the bi-directional Fowler-Nordheim tunneling effect,and the typical program/erase time is 10ms for every 16bits.A new,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme.The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.

Key words: RFID, single-poly, non-volatile memory, standard CMOS process, sense amplifier, low power