Abstract: This paper introduces a high-revolution,200kHz signal bandwidth ΣΔ modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability.Our design is realized in a standard 0.18μm CMOS process with an active area of 0.5mm×1.1mm.The ΣΔ modulator is driven by a single 192MHz clock signal and dissipates 5.88mW from 3V power supply.The experimental results show that,with an oversampling ratio of 48,the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR,and 80dB peak SNR in the signal bandwidth of 200kHz.

Key words: cascaded sigma-delta modulator, analog-digital converter, switched-capacitor circuits, operational amplifiers, CMOS analog integrated circuits