Super high maximum on-state currents in 2D transistors

Xiaotian Sun; Qiuhui Li; Ruge Quhe; Yangyang Wang; Jing Lu

doi:10.1088/1674-4926/43/12/120401

J. Semicond. > 2022, Volume 43?>?Issue 12?> 120401

NEWS AND VIEWS

Super high maximum on-state currents in 2D transistors

Xiaotian Sun^{1, X,}, Qiuhui Li^{3, X}, Ruge Quhe^2,, Yangyang Wang⁴ and Jing Lu^{3, 5, 6, 7, 8,}

+ Author Affiliations

1. College of Chemistry and Chemical Engineering, and Henan Key Laboratory of Function-Oriented Porous Materials, Luoyang Normal University, Luoyang 471934, China
2. State Key Laboratory of Information Photonics and Optical Communications and School of Science, Beijing University of Posts and Telecommunications, Beijing 100876, China
3. State Key Laboratory for Mesoscopic Physics and School of Physics, Peking University, Beijing 100871, China
4. Qian Xuesen Laboratory of Space Technology, China Academy of Space Technology, Beijing 100094, China
5. Collaborative Innovation Center of Quantum Matter, Beijing 100871, China
6. Beijing Key Laboratory for Magnetoelectric Materials and Devices (BKL-MEMD), Peking University, Beijing 100871, China
7. Peking University Yangtze Delta Institute of Optoelectronics, Nantong 226010, China
8. Key Laboratory for the Physics and Chemistry of Nanodevices, Peking University, Beijing 100871, China
Xiaotian Sun and Qiuhui Li contribute equally to this work.

Author Bio:

Xiaotian Sun is an Associate Professor at Luoyang Normal University. She received her Ph.D. degree in Material Science and Engineering at Soochow University. Her research interest focuses on 2D materials devices.

Qiuhui Li is a Ph.D. candidate at the Department of Physics, Peking University. She received her MS degree at the Department of Physics from the Beijing University of Posts and Telecommunications in 2019. Her research interests mainly focus on the electronic and transport properties of low-dimensional materials.

Ruge Quhe got her Ph.D. from Peking University. She is currently an Associate Professor with the School of Science, Beijing University of Posts and Telecommunications. Her research focuses on low-dimensional materials and electronics.

Yangyang Wang is an Associate Researcher at Qian Xuesen Laboratory of Space Technology, China Academy of Space Technology, Beijing. She received her Ph.D. degree in condensed matter physics from the Department of Physics, at Peking University, in 2016. She has been focusing on the research of electronic, optical, and transport properties of low-dimensional materials and their potential electronic and optoelectronic application.

Jing Lu is a Professor at the Department of Physics, Peking University. He was the ‘Hanjiang Scholars’ Project Distinguished Professor at Shaanxi University of Science and Technology, China. He is focused on exploring the properties of the two-dimensional (2D) semiconductor–metal interfaces, 2D semiconductors MOSFETs, and 2D materials optoelectronic devices by using the first-principles calculation and quantum transport simulations.

Corresponding author: Xiaotian Sun, xtsun2013@163.com; Ruge Quhe, quheruge@bupt.edu.cn; Jing Lu, jinglu@pku.edu.cn

DOI: 10.1088/1674-4926/43/12/120401

References

[1]	Liu Y, Duan X D, Shin H J, et al. Promises and prospects of two-dimensional transistors. Nature, 2021, 591, 43 doi: 10.1038/s41586-021-03339-z
[2]	Li M Y, Su S K, Wong H S P, et al. How 2D semiconductors could extend Moore's law. Nature, 2019, 567, 169 doi: 10.1038/d41586-019-00793-8
[3]	Wang Y Y, Liu S Q, Li Q H, et al. Schottky barrier heights in two-dimensional field-effect transistors: From theory to experiment. Rep Prog Phys, 2021, 84, 056501 doi: 10.1088/1361-6633/abf1d4
[4]	Quhe R G, Xu L, Liu S Q, et al. Sub-10 nm two-dimensional transistors: Theory and experiment. Phys Rep, 2021, 938, 1 doi: 10.1016/j.physrep.2021.07.006
[5]	Shen P C, Su C, Lin Y X, et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature, 2021, 593, 211 doi: 10.1038/s41586-021-03472-9
[6]	Liu L, Li T T, Ma L, et al. Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire. Nature, 2022, 605, 69 doi: 10.1038/s41586-022-04523-5
[7]	Ni Z Y, Ye M, Ma J H, et al. Performance upper limit of sub-10 nm monolayer MoS₂ transistors. Adv Electron Mater, 2016, 2, 1600191 doi: 10.1002/aelm.201600191
[8]	Wu R X, Tao Q Y, Li J, et al. Bilayer tungsten diselenide transistors with on-state currents exceeding 1.5?milliamperes per micrometre. Nat Electron, 2022, 5, 497 doi: 10.1038/s41928-022-00800-3
[9]	Sun X T, Xu L, Zhang Y, et al. Performance limit of monolayer WSe₂ transistors; significantly outperform their MoS₂ counterpart. ACS Appl Mater Interfaces, 2020, 12, 20633 doi: 10.1021/acsami.0c01750
[10]	Qiu C G, Zhang Z Y, Xiao M M, et al. Scaling carbon nanotube complementary transistors to 5-nm gate lengths. Science, 2017, 355, 271 doi: 10.1126/science.aaj1628
[11]	The International Technology Roadmap for Semiconductors (ITRS). Online available, https://irds.ieee.org/editions/2021
[12]	The International Roadmap for Devices and Systems (IRDS). Online available: https://ieeexplore.ieee.org/abstract/document/7046976
[13]	Natarajan S, Agostinelli M, Akbar S, et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm² SRAM cell size. 2014 IEEE International Electron Devices Meeting, 2014, 3.7.1 doi: 10.1109/IEDM.2014.7046976
[14]	Zhang Y C, Yu J, Zhu R X, et al. A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5?nm. Nat Electron, 2022, 5, 643 doi: 10.1038/s41928-022-00824-9

Fig. 1. (Color online) Benchmarking sub-100-nm bilayer WSe₂ transistors (red ball) against the (a) ${{I}}_{\text{on}}^{\text{max}}$ for 2D semiconductor transistors (b-P, b-As, b-AsP, MoS₂, MoS₂-0.7 nm, WSe₂-0.7 nm, WS₂, WS₂-0.7 nm, MoTe₂, GeAs, InSe, SnSe, ReS₂, PtSe₂, ZrSe₂, HfSe₂) and I_on of 2021 silicon transistor (black ball) reported in ITRS, and (b) the ${{R}}_{\text{on}}^{\text{m}\text{in}}$ (lowest on-state resistance) with those reported in the literature^[8]. Reproduced with permission from Springer Nature, copyright 2022.

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[1]	Liu Y, Duan X D, Shin H J, et al. Promises and prospects of two-dimensional transistors. Nature, 2021, 591, 43 doi: 10.1038/s41586-021-03339-z
[2]	Li M Y, Su S K, Wong H S P, et al. How 2D semiconductors could extend Moore's law. Nature, 2019, 567, 169 doi: 10.1038/d41586-019-00793-8
[3]	Wang Y Y, Liu S Q, Li Q H, et al. Schottky barrier heights in two-dimensional field-effect transistors: From theory to experiment. Rep Prog Phys, 2021, 84, 056501 doi: 10.1088/1361-6633/abf1d4
[4]	Quhe R G, Xu L, Liu S Q, et al. Sub-10 nm two-dimensional transistors: Theory and experiment. Phys Rep, 2021, 938, 1 doi: 10.1016/j.physrep.2021.07.006
[5]	Shen P C, Su C, Lin Y X, et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature, 2021, 593, 211 doi: 10.1038/s41586-021-03472-9
[6]	Liu L, Li T T, Ma L, et al. Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire. Nature, 2022, 605, 69 doi: 10.1038/s41586-022-04523-5
[7]	Ni Z Y, Ye M, Ma J H, et al. Performance upper limit of sub-10 nm monolayer MoS₂ transistors. Adv Electron Mater, 2016, 2, 1600191 doi: 10.1002/aelm.201600191
[8]	Wu R X, Tao Q Y, Li J, et al. Bilayer tungsten diselenide transistors with on-state currents exceeding 1.5?milliamperes per micrometre. Nat Electron, 2022, 5, 497 doi: 10.1038/s41928-022-00800-3
[9]	Sun X T, Xu L, Zhang Y, et al. Performance limit of monolayer WSe₂ transistors; significantly outperform their MoS₂ counterpart. ACS Appl Mater Interfaces, 2020, 12, 20633 doi: 10.1021/acsami.0c01750
[10]	Qiu C G, Zhang Z Y, Xiao M M, et al. Scaling carbon nanotube complementary transistors to 5-nm gate lengths. Science, 2017, 355, 271 doi: 10.1126/science.aaj1628
[11]	The International Technology Roadmap for Semiconductors (ITRS). Online available, https://irds.ieee.org/editions/2021
[12]	The International Roadmap for Devices and Systems (IRDS). Online available: https://ieeexplore.ieee.org/abstract/document/7046976
[13]	Natarajan S, Agostinelli M, Akbar S, et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm² SRAM cell size. 2014 IEEE International Electron Devices Meeting, 2014, 3.7.1 doi: 10.1109/IEDM.2014.7046976
[14]	Zhang Y C, Yu J, Zhu R X, et al. A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5?nm. Nat Electron, 2022, 5, 643 doi: 10.1038/s41928-022-00824-9