An extremely low power voltage reference with high PSRR for power-aware ASICs

Jihai Duan; Dongyu Deng; Weilin Xu; Baolin Wei

doi:10.1088/1674-4926/36/9/095006

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J. Semicond. > 2015, Volume 36?>?Issue 9?> 095006

SEMICONDUCTOR INTEGRATED CIRCUITS

An extremely low power voltage reference with high PSRR for power-aware ASICs

Jihai Duan, Dongyu Deng, Weilin Xu and Baolin Wei

+ Author Affiliations

Corresponding author: Xu Weilin, xwl@guet.edu.cn

DOI: 10.1088/1674-4926/36/9/095006

Abstract: An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18-μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3.3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm². The circuit can be used as an elementary circuit block for power-aware ASICs.

Key words: ASICs, extremely low power dissipation, high power supply rejection ratio, voltage reference source

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Fig. 1. Schematic of the proposed voltage reference.

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Fig. 2. Chip microphotograph of the proposed BGR.

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Fig. 3. Measured $V_{\rm ref}$ as a function of temperature, with a 2 V supply voltage.

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Fig. 4. Measured $V_{\rm ref}$ at room temperature as a function of power supply.

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Fig. 5. Measured PSRR at room temperature with a 2 V supply voltage.

DownLoad: Full-Size Img PowerPoint

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Table 1. Performance comparison of BGR.

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Received: 03 February 2015 Revised: Online: Published: 01 September 2015

Article Navigation > Journal of Semiconductors > 2015 > 36(9): 095006

Jihai Duan, Dongyu Deng, Weilin Xu, Baolin Wei. An extremely low power voltage reference with high PSRR for power-aware ASICs[J]. Journal of Semiconductors, 2015, 36(9): 095006. doi: 10.1088/1674-4926/36/9/095006 ****J H Duan, D Y Deng, W L Xu, B L Wei. An extremely low power voltage reference with high PSRR for power-aware ASICs[J]. J. Semicond., 2015, 36(9): 095006. doi: 10.1088/1674-4926/36/9/095006.

Citation:

Jihai Duan, Dongyu Deng, Weilin Xu, Baolin Wei. An extremely low power voltage reference with high PSRR for power-aware ASICs[J]. Journal of Semiconductors, 2015, 36(9): 095006. doi: 10.1088/1674-4926/36/9/095006 ****

J H Duan, D Y Deng, W L Xu, B L Wei. An extremely low power voltage reference with high PSRR for power-aware ASICs[J]. J. Semicond., 2015, 36(9): 095006. doi: 10.1088/1674-4926/36/9/095006.

Citation:

J H Duan, D Y Deng, W L Xu, B L Wei. An extremely low power voltage reference with high PSRR for power-aware ASICs[J]. J. Semicond., 2015, 36(9): 095006. doi: 10.1088/1674-4926/36/9/095006.

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An extremely low power voltage reference with high PSRR for power-aware ASICs

DOI: 10.1088/1674-4926/36/9/095006

Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology, Guilin 541004, China

Funds:

Project supported by the National Natural Science Foundation of China (Nos. 61161003, 61264001, 61166004) and the Guangxi Natural Science Foundation (No. 2013GXNSFAA019333).

More Information

Corresponding author: Xu Weilin, xwl@guet.edu.cn
Received Date: 2015-02-03
Accepted Date: 2015-04-02
Published Date: 2015-01-25

Abstract

Abstract

An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18-μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3.3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm². The circuit can be used as an elementary circuit block for power-aware ASICs.
- ASICs,
- extremely low power dissipation,
- high power supply rejection ratio,
- voltage reference source

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References

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An extremely low power voltage reference with high PSRR for power-aware ASICs

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